When using a 26 MHz crystal, we can disable the MPLL to go to sleep mode. When the crystal is replaced with a 26 MHz oscillator, the MPLL is not reliably disabled.
The Reference manual states:
The conditions to be satisfied before the PLL Clock Controller actually turns off the MPLL are as
1. Clock Controller module has successfully mastered the system bus.
2. The A9P_CLK_OFF signal from the ARM9 Platform is active.
3. SDRAM controller has successfully placed the external SDRAM into Self-Refresh mode.
4. After the above conditions are satisfied, the countdown based on the value in the SD_CNT field
will be initiated.
5. SD_CNT countdown completes.
What could prevent the Clock Controller module from successfully mastering the system bus?