Hi All,
we are working on processor P2041 with
*NOR flash device S29GL01GS10TFI010
*UART1 port of processor for console display
we have set the processor to hard coded RCW option ( RCW_CFG[0:4] = 1_1000 , 16-bit NOR Flash as boot location; dual 4-pin UARTs enabled; platform ratio of 6:1; core PLL ratio of 9 :1 ) and we have flashed the U-boot file (768KB) provided along with the P2041RDB at NOR location 0XEFF40000.We are not able to see the data on console display
-should the eLBC registers related to NOR in U-boot be edited for this problem?
-What are the parametrs need to be edited in the U boot for getting the display console ?
NOTE :we are not using the CTS and RTS of the UART1 PORT and have left those pins open
The Flash chip you are using is identical to the one used on P2041RDB,
therefore, if you did not alter the hardware connection, no eLBC-related
settings require adjustments. Regarding UART, the defauld baud rate
is set by CONFIG_BAUDRATE configuration macro which for P2041RDB is
115200. Hardware flow control is controlled by
CONFIG_SERIAL_HW_FLOW_CONTROL macro, this macro not set for P2041RDB
default u-Boot configuration.
Note, the programming addresses you mentioned are _not_ NOR flash addresses
which are only 27 bits long. They are full 32-bit local physical addresses as
configured by u-Boot. This address mapping is software-configured.
If you are using a JTAG debugger to program your Flash, the address
map it creates may be different. Consult at your debugger or Flash
programming tool intialization scripts for the local physical address
map it establishes. u-Boot must be programmed in the upper 768KB
of the boot Flash.
Have a great day,
Platon
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