I'm interested in disabling all SEC-DED measures in flash and SRAM (correction and detection). Is it possible? Excuse if the question is trivial, but I'm not sure it is possible after having read documentation.
So, basically, the only thing i can enable/disable is reporting (z4 core).
- Yes, only ECSM reporting can be enabled/disabled.
Does this mean an access in a location with ECC single bit error causes the flash to be overwritten with corrected value (thus charge pump in flash is activated to write as a normal writing)?
- No, it does not perform any flash write. Single bit flash error remains in the flash memory unless user software physically corrects it (re-programs), but it is not necessary as data affected by single bit error are automatically corrected during read => internal data bus contains right data and application can work normally.
Multi-bit error leads in IVOR1 exception as SEC-DEC code does not have capability to CORRECT more than 1 bit error during read, but it is capable to DETECT multi-bit error. Multi-bit error response (IVOR1 handler) is purely application dependent and it is up to user application, how it’ll be treated.
ECC logic cannot be disabled. Core reading or executing of data affected by multibit ECC error always lead in IVOR1/2/3/checkstop according to particular core variant (for e200z4 only IVOR1).
See following document, chapter 3:
Thanks for the quick reply, I've read the app note now. So, basically, the only thing i can enable/disable is reporting (z4 core).
This is a very crucial point to me, so I want to be very sure. I know what i'm asking for is not conventional too, for this type of safe controllers.
My application has the tight requirement of no writing in flash (just reading).
Retrieving data ...