I am currently working on MPC5668g, where its a dual core with two mode of INTC. In that I am working on hardware vector mode in z6 core(with 128Mhz as system clock). I need few clarifications about hardware vector mode. In this mode, when two interrupts occurs at same time or an interrupt is occurring when one ISR is getting processed, this hardware vector mode will queue the another interrupt or will ignore that corresponding interrupt if it is low priority?.
Please drop your suggestions and please share any document available for hardware vector mode in detail.