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ADC Clock Divide Select from the register ADC0_CFG1.

Question asked by AITOR ARANZABAL on Oct 26, 2015
Latest reply on Oct 28, 2015 by AITOR ARANZABAL

Hello all,

 

I have a FRDM-KL25Z and I am working with the ADC.

I configure the ADC_LDD component with the PE, to make it to work in continuous measuremente mode with interrupts. I save the results of the ADC conversions into an array.

The PE defines  the Clock Divide Select bits from the ADC0_CFG1 register as input clock/2 (ADIV = 01) . However I am interested to make the conversiones as fast as possible, so I change the register value manualy to input clock/1 (ADIV = 00).

 

I use a led pin to see the time that needs 3000 measurements by the oscilloscope, and I see that there is no difference when I change ADIV to 00.

In both cases it need 7.13ms for 3000measuremente (2.37us per measure). How is that possible? Should not be a difference when the ADC clock is changed?

Please find below my code.

ADC Clock prescaler.png

 

 

And this is the interrupt routine:

 

 

ADC Clock prescaler 2.png

 

Thank you in advance. Any help will be appreciated.

Aitor.

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