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Frequency compensated clock out timing diagrams

Question asked by Kaushal Sanghai on Jan 8, 2008
Latest reply on Jan 8, 2008 by Alan Bartky

I am wondering if someone can provide the timing diagram of the prescale clock out of the IEEE 1588 engine in the QUICC architecture. The timing diagrams are not covered in the HRM or in the data sheets. Since the engine uses a frequency compensated clock to adjust the timing of the counter, I am not sure how the output clock will look like. Will we need additional PLL circuitry to get a clean 50% duty cycle clock?