I am trying to make Windriver Vxworks 5.5.2 running on Core#3 of T2080 Soc (AMP mode). My platform is T2080RDB board from FreeScale.
Now I can boot the vxworks 5.5.2 on core#3 from U-boot with this command:
# tftpboot 0x20100000 vxWorks.bin && cpu 3 release 0x201002e8 6 1 1
I reserve the RAM from 0x20000000 - 0x3FFFFFFF (512MB) for Vxworks running on Core#3, so I setup one TLB1 entry 1 to map 0x0 -> 0x20000000, 512MB.
The Vxworks 5.5.2 is built with Text segment is set to 0x100000
The issue is that the Instruction Address Translation for T2080 does not work but the Data Address Translation for T2080 works.
When execute code from any address in 0x1xxxxx (For example: TLB mis handler ... ), the Core#3 always get 0xDEADBEEF (The reset value of RAM) for instruction.
I use Codewarrior to debug the system and I found that the Data Address Translation works, I can read the value at that memory correctly (not 0xDEADBEEF).
It seems that E6500 Core#3 does not care about TLB when making Instruction Address Translation.
Is this an errata of Chip ? How could I overcome this ?