Karen Shi

How to distinguish the reset caused by pulling /RESET low vs. the reset caused by power on - MC9S12DJ64

Discussion created by Karen Shi on Dec 5, 2007
Latest reply on Dec 7, 2007 by Xbot
On my project, 9S12DJ64 is used. Cosmic compiler is the compiler I am using. In my code, I need to do different actions during the reset upon the reset was caused by pulling /RESET pin down (soft reset or external reset) or power loss (i.e. power down then power on). I am not sure how can I  detect the difference. At Freescale document CRG Block User Guide, v04.05, section 5.2.3 discussed about power on reset and low voltage reset. But  at Figure 5-2 and Figure 5-3, /RESET pin was shown at the timing diagram. I also didn't know what is "Internal POR" and "Internal /RESET" means at those timing diagram. At section 3.3.4, CRG Flags Register (CRGFLG), bit PORF is power on reset flag. It said that PORF is set to '1' when a power on reset occurs. I tried to read this bit at my board, it always read back '0' no matter if I cycle the power (power down then up) or pull /RESET pin to low. I hope I can get your help on this issue.
Thank you very much and very appreciate for any suggestion / comment.
Added p/n to subject.
Karen Shi

Message Edited by NLFSJ on 2007-12-05 03:58 PM