AnsweredAssumed Answered

Problem with address bit 13 when accessing MRAM on TWRMEM module

Question asked by Jacky Lau on Jul 29, 2015
Latest reply on Jul 31, 2015 by xiangjun.rong

I’ve encountered  an issue with the MRAM access when running a memory device test.

 

I’ve purchased three tower boards – the main board, the serial communication board (TWRSER) and the memory board (TWRMEM). I put the three boards together and run a memory test code on the MRAM through flexbus (print out the result on UART3). I followed the flexbus configuration and MRAM access code from AN4393. When I run the memory write and read-back test, all memory location on the MRAM runs fine except when bit 13 of the address line is high. Any location with address bit 13 high always read back a value of 0xAD. (Anything in the range of X2XXX to X3XXX, X6XXX to X7XXX, XAXXX to XBXXX, XEXXX to XFXXX).

 

From the pattern of the error, it would look like bit 13 of the address bus (PTC1) is triggering something that cause the data bus to go 0xAD?

Here are the versions of boards and the jumper setting that I’m using:

Mainboard: 700-26548 REV E (I'm using TWN-K60N512)
J1 ON,  J6 1-2,  J8 ON,  J9 1-2,  J12 ON

TWR-MRM: 700-26248 REV A
J1 1-2,  J3 1-2,  J4 1-2,  J10 ON,  J12 1-2,  J13 ON,  J14 1-2,  J15 ON,  J16 2-3

 

TWR-SER: 700-26004 REV E
J2 1-2,  J15 1-2,  J16 1-2,  J17 1-2,  J19 1-2

Here are the flexbus configuration that I use (same as AN4393):

#define MRAM_CSAR_BA (*(UTiny*)(0x60000000))    /* Chip Select Address for MRAM - use non-cacheable region*/
#define MRAM_CS         (0)             /* Chip Select index for MRAM peripheral */
#define MRAM_CSMR_BAM   (0x07)          /* Base Address Mask for MRAM. 0x07 represent a memory range of 512kb */
#define MRAM_CSMR_WP    (0)
#define MRAM_CSMR_V     (1)             /* CSAR, CSMR and CSCR are valid */
#define MRAM_CSCR_SWS   (0)
#define MRAM_CSCR_SWSEN (0)
#define MRAM_CSCR_EXTS  (0)
#define MRAM_CSCR_ASET  (1)
#define MRAM_CSCR_RDAH  (0)
#define MRAM_CSCR_WRAH  (0)
#define MRAM_CSCR_WS    (1)             /* Wait state is 1 */
#define MRAM_CSCR_BLS   (1)
#define MRAM_CSCR_AA    (1)             /* Automatic Acknowledge enabled */
#define MRAM_CSCR_PS    (1)             /* Port size is 8 bit */
#define MRAM_CSCR_BEM   (0)
#define MRAM_CSCR_BSTR  (0)
#define MRAM_CSCR_BSTW  (0)

Here are part of the memory test result:

Address bus test begin...Write 00000055 to power of 2 addresses.
00000001 passed. W:00000055 R:00000055

00000002 passed. W:00000055 R:00000055

00000004 passed. W:00000055 R:00000055

00000008 passed. W:00000055 R:00000055

00000010 passed. W:00000055 R:00000055

00000020 passed. W:00000055 R:00000055

00000040 passed. W:00000055 R:00000055

00000080 passed. W:00000055 R:00000055

00000100 passed. W:00000055 R:00000055

00000200 passed. W:00000055 R:00000055

00000400 passed. W:00000055 R:00000055

00000800 passed. W:00000055 R:00000055

00001000 passed. W:00000055 R:00000055

00002000 failed. W:00000055 R:000000AD

00004000 passed. W:00000055 R:00000055

00008000 passed. W:00000055 R:00000055

00010000 passed. W:00000055 R:00000055

00020000 passed. W:00000055 R:00000055

00040000 passed. W:00000055 R:00000055

I’ve also run another memory test with bit 13 low all the time – and all other memory location passed the write-readback test.

 

The TWRMEM's new and I doubt it is faulty. Could there be jumper setting that I'm not aware of? Conflicts between the three boards? or something in the software setting (not mentioned in AN4393)?

 

Thank you for your help!

Outcomes