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PCIe: RC cannot write into EP

Question asked by Elijah Brown on Jul 8, 2015
Latest reply on Nov 24, 2015 by Carl Jackson
Branched to a new discussion

The IMX6 is configured as a PCIe EP, which is connected to a RC (not an IMX6).  I've got two iATU configurations, as follows:

 

    pcie_map_inbound_addr(PCIE_IATU_VIEWPORT_0,

                                            TLP_TYPE_MemRdWr,

                                            (uint32_t)endpointBuffer,

                                            0x90500000,

                                            SZ_64K);    

 

    pcie_map_outbound(PCIE_IATU_VIEWPORT_1,

                                          TLP_TYPE_MemRdWr,

                                           PCIE_ARB_BASE_ADDR,

                                           0x310000,

                                           SZ_64K);

 

 

Here's what the inbound mapping function does:

 

uint32_t pcie_map_inbound_addr(uint32_t viewport, uint32_t tlp_type,

                               uint32_t addr_base_cpu_side, uint32_t addr_base_pcie_side, uint32_t size)

{

    // configure as an inbound region

    HW_PCIE_PL_IATUVR_WR((viewport & 0x0F) | (1 << 31));

 

    // configure region's base and limit address

    HW_PCIE_PL_IATURLBA_WR(addr_base_pcie_side);

    HW_PCIE_PL_IATURUBA_WR(0);

    HW_PCIE_PL_IATURLA_WR(addr_base_pcie_side + size - 1);

 

    // configure target address

    HW_PCIE_PL_IATURUTA_WR(0);

    HW_PCIE_PL_IATURLTA_WR(addr_base_cpu_side);

 

    // configure TLP type

    HW_PCIE_PL_IATURC1_WR(tlp_type & 0x0F);

 

    // enable region

    HW_PCIE_PL_IATURC2_WR(((unsigned int)(1 << 31)));

 

    return addr_base_cpu_side;

}

 

Bus mastering is configured in the EP.  The outbound transactions (EP to RC) work fine, I can read and write memory in the RC by reading or writing PCIE_ARB_BASE_ADDR.  But the other way around, inbound transactions (RC to EP) doesn't work.  The RC is sending TLPs with address 0x90500000, which I want to map into the IMX's DRAM, specifically a 64K buffer named endpointBuffer.  This buffer is 1M aligned to meet the iATU requirements of 64k aligning and the MMU requirements of 1M aligning so I can turn caching off for it... The RC sets BAR0 to 0x90500000 and BAR2 to 0x310000.  For whatever reason I can't make the BAR1 mask anything non-zero so I'm using BAR2 instead. 

 

What am I missing?  The fact that outbound transactions are working makes me think this has to be close, and just an error in the mapping.  I've tried setting up the inbound mapping to do BAR matching and address matching, neither seems to work.

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