AnsweredAssumed Answered

PCI Express "phy never came up" with BSP 3.10.17_1.0.2-GA, custom board

Question asked by Jonas Höppner on May 27, 2015
Latest reply on Jun 29, 2015 by Jonas Höppner

Hello everybody,

 

We have desisgned a custom board with the imx6 dual, where the pci express is used to connect an Exar PCI Express UART (XR17V358).

Out software is based on the Freescale Yocto BSP 3.10.17_1.0.2-GA.

 

On some boards there a startup problems where the pci express link is not always comming up ("phy never came up" in boot log).

Adding additional debug messages, are showing that the LTSSM stays in DETECT and POLLING states.

I have seen those other threads regarding pcie, but couldn't find a solution yet ( except from upgrading to a newer release, which we haven't tried yet).

 

I've measured the pcie signals and could clearly see the difference between the cases where the link comes up and those where not.

In the cases it is working, all signals looked like valid PCIe signals (Z1, yellow), as far as I can tell with 600MHz bandwidth, when the link does not come up,

both tx signals are looking totally different ( Z4 green).
(There are two different measurements from two boot processes show, both on the same tx line, the reduced level of the high speed parts are probalbly related to the bandwidth of the scope).

As the signal is clearly broken, I don't think we are seeing signal problems that can be handeled by changing the IOMUXC_GPR8 register as mentioned here: AN4784

txzoom1.png

How often the error is happening, is related to the temperature:

One PCB that has the error in most cases at about 23 degree Celsius, starts successful cooled down with colling spray.

Another, after some fixes to the ldo bypass mode, starts successfully a room temperature but fails below 5 degree Celsius.

Other boards don't show any problems between 55 degree and -25 degree Celsius.

It seems also somehow related if the chips is powered in ldo bypass mode or in ldo mode.

 

This is, why my guess is, that the pcie phy is not comming up, may be because of unstable clocks.

 

What currently seems to improve the stability, is enabling the pcie_ref_125m clock very early with adding:

    clk_prepare_enable(clk[pcie_ref_125m]);

to the end of imx6q_clocks_init().

 

Any hints, on how we might get this stabilized?

 

Regards, Jonas

Outcomes