AnsweredAssumed Answered

fsl_ftm bug on 100Hz?

Question asked by Massimiliano Sturla on Mar 23, 2015
Latest reply on Feb 25, 2016 by juanruiz

Hi to all,

I'm trying to generate PWM signal starting from fsl_ftm component.

developing with KDS 2.0.0 and KSDK 1.1.0 on K20 device (i'm using K60 for PEx because KSDK for k20 is not ready yet)

 

I want to generate a PWM with frequency 10 Hz and 50 duty cycle

setting of PEx flex timer are:

device FTM0

counter FTM0_CNT

basic config: overflow= 0, write protection disable, BDM = zero mode, SW trigger enabled and disabled all HW trigger

pwm chan config: Freq= 10 Duty=50,  Edge mode= high true. mode= edge alligned pwm

quadrature disabled

pin, all disabled (fault all disabled; external clock pin disabled, HW sync disabled)

init: timer overflow interrupt and fault interrupt disabled

PWM channel: #2 ---> Pin PTA5

 

If I use Freq > 400 Hz all work right... but if I set 100 Hz (more then my 10Hz wanted) i see a PWM of  about 550 Hz....

 

Why this problem occours?

thanks,

Massimiliano

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