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UART FIFO appears empty even though it is not (K64 & MQX 4.1)

Question asked by Tim Meyer on Feb 12, 2015
Latest reply on Dec 5, 2018 by Richard Rapier



I have a somewhat rare issue with my UART RX FIFO. The K64 UART is connected to a half duplex RS485. I haven't pinned down exactly how to cause the issue yet, but it seems to occur more frequently when I send lots of contiguous serial data. If I had to guess, it would be caused by a bit r framing error on the UART bus.



- K64 & MQX 4.1

- UART1 interrupt mode (8N1 @ 115200)

- RTS pin controls RS485 flow control (flag: IO_SERIAL_HW_485_FLOW_CONTROL)


The symptom:

Once the issue occurs, it never seems to go away until I reset the K64. As an example: the master will send a packet of say 10 bytes  to the k64 slaves on the rs485 bus. Then the k64 will read one byte at a time from the UART driver. The following function is used to determine if data is ready to be read:

     _io_ioctl(port, IO_IOCTL_CHAR_AVAIL, &ready);

When the issue occurs, I can read say 6 bytes from the UART buffer, and then ready becomes FALSE, even though there is still 4 more bytes that should be ready. This function will continue so indicate no data is ready until an additional byte is sent by the master, in which case I will be able to ready 1 more byte from the UART driver.


It seems as if the data is stuck in the FIFO, but is not accessible. I have put a sniffer on the bus to confirm that the data wasn't being cached in the master side UART and can see all the data on the bus. I've also had multiple k64's on the same bus all receiving the same data and some of the K64s will receive all the data properly and others will get into this erroneous state.


Seems to be related to: K22 MXQ4.02 serial port will miss characters if paste a lot of commands together(cause overflow and RX_OVERRUNS)


Any help would be appreciated.