The P1010RDB-PB eval platform has an available USB clock source generated by the IDT ClockGen (U13).
Was there a compelling reason to add a separate external oscillator (Y2) to generate the USB PHY clock?
The P1010 USB requires 24 MHz clock source and jitter below 5ps. The 6V49205BNLGI does not provides similar jitter for 24MHz clock generation. The 6V49205BNLGI 24MHz jitter is 350ps. See the The 6V49205BNLGI Datasheet (http://www.idt.com/document/dst/6v49205b-datasheet).
The Section 2.12.3 of the P1010 Datasheet Rev 4 contains USB PHY clock requirements. The better solution for these requirements is a separate external oscillator (Y2) to generate the USB PHY clock.
I am asking why the IDT ClockGen (U13) USB clock was not used. It is available and meets the specification.
Why is a dedicated oscillator a better solution? Is there an undisclosed issue with the IDT part?
Would it not be the RMS jitter of 120ps max that is the culprit. I'm considering a part with 5ps RMS jitter and 50ps pk-pk jitter. The P1010 datasheet doesn't specify a peak to peak jitter requirement.
The USB 2.0 Specification requires BER<= 10E-12. It corresponds the peak to peak jitter about 70 ps.
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