i.MX6Q video capture issue with ADV7280-M

[stathisv]

Hello,

I have the VAR-SOM-MX6 custom board from Variscite and the ADV7280-M EVM.

The I2C and MIPI lines of the 2 boards are connected in order to capture video.

The ADV7280-M has been configured to use VC1 and is therefore routed to CSI-1.

I am trying to use the Freescale mxc_v4l2_capture.out application to capture into a file.

However, no frames become available for dequeing and when I print out the contents

of the MIPI_CSI_ERR1 register bits 0 (start of TX error on data lane 0) and 28 (header

ecc contains 2 errors) are set. The contents of MIPI_CSI_PHY_STATE indicate that

the MIPI clock from the video decoder is being detected.

Is this just down to H/W (cabling issues) or some configuration issue?

The video decoder outputs interlaced video and the MIPI clock rate is 108 MHz.

Is there some clock setting on the i.MX6 side that needs to be configured to match that?

Thank you,

Stathis

[peteramond]

Dear stathisv

Can you help me on following ?

I'm using the ADV7280M chip in a new design. Currently I have a IMX6 Quad Sabre Lite development board and I'm trying to decode one CVBS input to feed iMax MIPI using the circuit which I was made from ADV7280M. I connected ADV7280M with iMAX6 using I2C and MIPI data lane.Also, I have Linux distribution that has an adv7180_mipi.c driver.

1.       Does this driver compatible with ADV 7280M ? Does Analog Devices have a Linux driver for ADV7280M ? Are you aware of any other driver support or how this driver can be used to stream video from the ADV7280M ? Can you tell me the way of combining ADV7280M with Video 4 Linux architecture ?
2.       As well as it is not possible to run the script given here ADV7280 / ADV7280-M Design Support Files | EngineerZone  for ADV7280M development board as I have made my PCB using only ADV7280M chip. There is no usb data communication and I'm just using I2C and MIPI data and clk pins of the chip to communicate with iMAX6. So I need to address the registers of the ADV7280M chip in a different way( Not like in Script). So can you tell me how should I address for each and every registers of the chip using I2C or provide some reference materials ?

Thank You,

Peter.

[kurkinalexandr]

Uploaded my driver for Linux 3.0.35. Basic functionality works. Let me know if smth unclear.

[arslan]

Hallo Stathis,

Would you please share yor driver? I am also trying to interface adv7280-m with imx6q. The driver with kernel 4.1.15 does not work with imx6.

Thanks

Hasan

[wojtekbe]

Hello everyone,

I am also facing the problem of capturing frames from ADV7280M. I am using custom encoder board connected to IMX6q module from Toradex, which was tested and worked fine with other SOC (Tegra3).

Currently I'm using modified ov5640_mipi driver (with 3.10.17 kernel) and configure the ADV7280M to work in free-run mode with colorbars (480p). I've only changed the virtual channel to 1 (0x0D MIPI-CSI register)

When I try to capture an image I use gstreamer:

gst-launch -v mfw_v4lsrc device=/dev/video2 capture-mode=1 ! mfw_v4lsink

and I am getting a timeout error:

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

No sync interrupts appeared (iMX6 register IPUx_INT_STAT_1 = 0), no CSI errors occured (MIPI_CSI_ERR1 = MIPI_CSI_ERR2 = 0),

bit 8 of MIPI_CSI_PHY_STATE is 1, which means the pixel clock is being received properly.

I would also deeply appreciate any patches or hints....

Thanks,

Wojtek B.

[faisaltaj]

Hi everyone,

I would deeply appreciate if someone can upload a patch file for the changes that are required to be made in the kernel to capture video via mipi interface from ADV-mipi video decoder. Kind of facing similar issue.

Thanking in advance.

Faisal

[saurabh206]

Hi

Stathis

Please go through the

Debug steps for customer MIPI sensor.docx

Thanks

Saurabh

[stathisv]

Hi Saurabh,

Thank you for the link. I wonder if you could clarify for me section C.2 of the doc

regarding the writes in PHY_TST_CTRL1 register as they are not documented in

the i.MX6 RM. The MIPI-CSI2 driver in our kernel does the following writes:

PHY_TST_CTRL0 = 0x00000001

PHY_TST_CTRL1 = 0x00000000

PHY_TST_CTRL0 = 0x00000000

PHY_TST_CTRL0 = 0x00000002

PHY_TST_CTRL1 = 0x00010044

PHY_TST_CTRL0 = 0x00000000

PHY_TST_CTRL1 = 0x00000014

PHY_TST_CTRL0 = 0x00000002

PHY_TST_CTRL0 = 0x00000000

According the doc for a MIPI clock of 108 MHz the value of 0x40 needs to be

written to PHY_TST_CTRL1, but how does that fit in the above sequence?

Thanks a lot,

Stathis

[igorpadykov]

Hi Stathis

one can look also

Some Experience When Enable MIPI Camera

Best regards

igor

[stathisv]

Thank you Igor,

I had seen that thread and it actually helped me to configure the MIPI-CSI2 DPHY

correctly to match the frequency of the ADV7280-M MIPI clock.

I can now grab frames but the video is not correct and bit 0 of IPU_INT_STAT_5

gets set, meaning a new frame before end-of-frame error. Do you have any tips on

what may cause that?

From what I can see the IPU clock is running at 264 MHz and the pixel clock

at 198 MHz.

My path is to capture video through CSI1 to memory, without going through the IC.

Best regards,

Stathis

[yurykocherov]

Hi Stathis,

Looks like I have a same problem that you solved. What value did you set in the "PHY_TST_CTRL1" register?

- When I set 0x40 (108 MHz) I have an error in the MIPI_CSI_ERR1 register.

- When I set 0x26 (216 MHz) - MIPI_CSI_ERR1 is cleared.

Looks like it is necessary to set double freq...

Regards, Yury.

[stathisv]

Hi Yury,

That's correct. The value that you set in PHY_TST_CTRL1 corresponds to the received bit rate.

Since the MIPI link captures at double data rate (DDR), ie both edges of the clock, the bit rate

will be double the clock rate.

Regards,

Stathis

[yurykocherov]

Hi Stathis,

Thank you very much! It gives me one more correct value!

Regards, Yury.

[stathisv]

Hi Yury,

You are welcome! Have you got video capture working now with the ADV7280-M?

I wonder if I could ask you about a strange issue that I see.

1) I program the device registers and enable MIPI TX by writing 0x00 to CSI reg[0x00] on the ADV7280-M

2) From that point it starts capturing frames OK

3) If I do a register read on the ADV7280-M (eg STATUS1) it seems to stop capturing any more frames.

That is, if I read a register while MIPI is active then it does not give me any more frames.

The I2C read itself succeeds and returns the expected value.

Regards,

Stathis

[yurykocherov]

Hi Stathis,

Yes, I have started capturing via adv7281-m. :smileyhappy:

Regarding your question: I don't work with I2C line after enable MIPI TX (writing 0x00 to CSI reg[0x00]). I will try to repeat it on my equipment.

One question, do you have captured video correct? Because I see that my video scrolling vertically time to time... I am capturing NTSC video (adv7281m in auto detect mode) so dimensions are 720 x 480. IPU registers shows:

[54820.153681] imx-ipuv3 imx-ipuv3.0: IPU1_INT_STAT_1 =     0x08800000

[55331.874591] imx-ipuv3 imx-ipuv3.0: CSI_SENS_CONF =    0x04000A00

[55331.874609] imx-ipuv3 imx-ipuv3.0: CSI_SENS_FRM_SIZE = 719 x 524

[55331.874627] imx-ipuv3 imx-ipuv3.0: CSI_ACT_FRM_SIZE = 719 x 479

These values I see every time and when video scrolling, and when video normal.

Have you seen something like this?

Regards, Yury.

[stathisv]

Hi Yuri,

No, I did not have any problem with scrolling lines. It could be a vertical locking issue maybe?

You could configure the adv7281-m in free-run mode with the boundary box pattern and

check if that works OK or you see the white line of the pattern scrolling. It that is all OK it could

be your video source to blame.

I would really appreciate it if you could do a quick test for my issue, although your device is

slightly different. You could just add in your driver a read of eg. the STATUS1 register just

after you enable MIPI TX. If I do that I do not get any video.

Thanks,

Stathis

[yurykocherov]

Hi Stathis,

I have done this short test. My result - all works OK. Below my debug output:

1) Power-up MIPI part of AFV7281-M:

[   80.815408] ADV7280: Dbg: adv7280_write_config[0]: reg = 0xde, value = 0x02

[   80.823417] ADV7280: Dbg: adv7280_write_config[1]: reg = 0xd2, value = 0xf7

[   80.832851] ADV7280: Dbg: adv7280_write_config[2]: reg = 0xd8, value = 0x65

[   80.840092] ADV7280: Dbg: adv7280_write_config[3]: reg = 0xe0, value = 0x09

[   80.847676] ADV7280: Dbg: adv7280_write_config[4]: reg = 0x2c, value = 0x00

[   80.855104] ADV7280: Dbg: adv7280_write_config[5]: reg = 0x00, value = 0x00          (with pause 255 ms after)

2) Readout iMX MIPI status:

[   81.130975] ADV7280: Trace: adv7280_wait_mipi_ready

[   81.135871] ADV7280: Dbg: mipi_csi2_dphy_status = 0x0300

[   81.141233] ADV7280: Dbg: mipi_csi2_error1 = 0x0000

[   81.146900] ADV7280: Dbg: mipi_csi2_error2 = 0x0000

3) Readout ADV7281-M status:

[   81.151837] ADV7280: Trace: adv7280_show_status

[   81.156970] ADV7280: Dbg: Status1 = 0x0D

[   81.161519] ADV7280: Dbg: Status2 = 0x00

[   81.165724] ADV7280: Dbg: Status3 = 0x69

4) Readout iMX MIPI status:

[   81.169659] ADV7280: Trace: adv7280_wait_mipi_ready

[   81.174588] ADV7280: Dbg: mipi_csi2_dphy_status = 0x0300

[   81.180424] ADV7280: Dbg: mipi_csi2_error1 = 0x0000

[   81.185708] ADV7280: Dbg: mipi_csi2_error2 = 0x0000

And after that I can see captured image.

Regards, Yury.

[stathisv]

Hi Yury,

Thanks for doing the test.

What I get in step 4 is DPHY status 0x0200, meaning that the i,MX does not see a clock any more.

I think it is a H/W issue, we improved the grounding between the 2 boards and now it does

seem to work occasionally.

Stathis

[igorpadykov]

Hi Stathis

I think you can decrease frame rate from sensor

so IPU had time to process frames.

~igor

[stathisv]

Hi Igor,

Thank you for your reply.

The sensor is capturing NTSC resolution at either 60 fields/sec or 60 frames/sec,

ie I have tried both interlaced and progressive output from the sensor, as it has that option.

As explained earlier the MIPI clock rate fro the sensor is 108 MHz for interlaced or 216 MHz

for progressive.

According to the Freescale doc mentioned earlier in this thread, the IPU and pixel clock that

I have should be fast enough?

Thanks,

Stathis

[igorpadykov]

Hi Stathis

this may depend on processor bus loading, so this frequency may not

be sufficient.

~igor