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Question about gated clock mode

Question asked by zhou wei on Nov 13, 2014
Latest reply on Sep 26, 2016 by li wuxiang

Hello

     I am using i.mx6 to capture 16bit 4:2:2 YUV signal in gated clock mode. but it does not work like what the datesheet says.

     it is said"Pixel clock is valid as long as IPU2_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. IPU2_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream.in IMX6DQCEC(section 4.11.10.2.2 Gated Clock Mode). But real situation is that imx6 would capture data when the rising edge of Hsync comes, and imx6 would not stop capturing data even the falling edge comes.There may be something wrong.

     i haven't found someone using imx6 to capture data correctly in gated clock mode in this community but found many peopel facing the same problem.

     If  there is someone using imx6 to capture data correctly in gated clock mode, could you tell me and give me some advice?


Thanks !

 

zhou

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