The questions about SPI

[小勇邹]

I have read the SPI example in the address.

C:\Freescale\Freescale_MQX_4_1_TWRK64F120M\mqx\examples\spi

I have 3 questions:

1, What is the meaning of the parameter “cs_mask” in callback
function “set_CS”? Which parameter is transferred to the parameter “cs_mask” in
this example?

2, My SPI application has 1 master and 4 slavers (select
signals:CS0,CS1,CS2,CS3). How to select the slaver?Do I have to select the slaver in the callback
function? If I want to communicate with the slavers one by one, how should Imodify the source code?

3,The document < MQX_IO_User_Guide.pdf > Page 63
describes that

“the chip select signals are de-asserted and the bus is
released by execution of either IO_IOCTL_FLUSH_OUTPUT or IO_IOCTL_SPI_FLUSH_DEASSERT_CS command or by closing the file handle with _io_close() call.”

If I select the chip in the callback function by myself, are
the chip select signals still de-asserted by execution of either IO_IOCTL_FLUSH_OUTPUT
or IO_IOCTL_SPI_FLUSH_DEASSERT_CS command or by closing the file handle with
_io_close() call?

[小勇邹]

Thank you very much. I still have some questions according to your answer.

1)

As it is written in MQX_IO_User_Guide.pdf, cs_mask will tell
you how to set chip select pins.

So, if you open SPI1:1 and SPI1:8, cs_mask will give you one
followed of numbers - 1,8 or 0 (it depends on type of even which causes calling
set_CS()). 0 has special meaning and it means that you have to set all CS pins
to inactive state (typically high level).

cs_mask doesn’t need to be directly mask, it could be any
number. So, you can open SPI1:22 and when you write to this interface, cs_mask
will contain number 22. Note: this is valid only for case when we use software
callback.

In the example,spifd = fopen ("spi0:", NULL);

What is the value of cs_mask in the example?(C:\Freescale\Freescale_MQX_4_1_TWRK64F120M\mqx\examples\spi)

2)

Yes, you should set all CS pins in “set_CS” function. set_CS() function is always just one. cs_mask will tell you how to set your CS pins. You don’t need modify the source code. You can do for example:

Spifd1 = fopen (spi1:1, NULL);

/*Does it mean that cs_mask is set as 1*/

Spifd2 = fopen (spi1:2, NULL);

Spifd3 = fopen (spi1:4, NULL);

Spifd4 = fopen (spi1:8, NULL);

…

result = fwrite (buffer1, 1, 1, Spifd1);

/*Does it means the function will call the callback function "set_CS()"?Does it mean that I shoud set the CS0 as 0(select the chip) and the other signals as 1 in the  callback function "se_CS()"?*/

result = fwrite (buffer2, 1, 1, Spifd2);

result = fwrite (buffer3, 1, 1, Spifd3);

result = fwrite (buffer4, 1, 1, Spifd4);

You typically call Spifd1 from different task than Spifd3, SPI driver is prepared for that situation and only one from SpifdX could be bus owner at the same time, others must wait until task executes fflush (SpifdX);.

3)

Yes, any call IO_IOCTL_FLUSH_OUTPUT (fflush (SpifdX);) or IO_IOCTL_SPI_FLUSH_DEASSERT_CS command or by closing the file handle with _io_close() (in this case it depends on who is currently owner of SPI bus) will call “set_CS” function.

/*Does it mean that fflush and _io_close() function will  set cs_mask as 0 and transfer it to the “set_CS” function and I should set all the signals as 1 in the function(de-asserted all the chips)?*/

4)If the task call  fwrite (buffer2, 1, 1, Spifd2),does it mean that the ask should wait until the SPI completes the data transmission?

Is there interrupt method for read and write SPI? For example,the task sleeps after calling fwrite and it wates up after the SPI completes the data transmission.

[RadekS · Accepted solution]

See my blue answers:

1)

As it is written in MQX_IO_User_Guide.pdf, cs_mask will tell
you how to set chip select pins.

So, if you open SPI1:1 and SPI1:8, cs_mask will give you one
followed of numbers - 1,8 or 0 (it depends on type of even which causes calling
set_CS()). 0 has special meaning and it means that you have to set all CS pins
to inactive state (typically high level).

cs_mask doesn’t need to be directly mask, it could be any
number. So, you can open SPI1:22 and when you write to this interface, cs_mask
will contain number 22. Note: this is valid only for case when we use software
callback.

In the example,spifd = fopen ("spi0:", NULL);

What is the value of cs_mask in the example?(C:\Freescale\Freescale_MQX_4_1_TWRK64F120M\mqx\examples\spi)

If you do not specify CS number/mask, CS0 will be automatically used (strtoul() function is used for read CS number)

2)

Yes, you should set all CS pins in “set_CS” function. set_CS() function is always just one. cs_mask will tell you how to set your CS pins. You don’t need modify the source code. You can do for example:

Spifd1 = fopen (spi1:1, NULL);

/*Does it mean that cs_mask is set as 1*/

Fopen will not call set_CS function, but you are right. Spifd1 will use number 1 as CS signal. So, if you will write into Spifd1, cs_mask will contain number 1. Therefore set_CS function has to set appropriate pin combination for appropriate chip select. This could be used for example when you connect external 1-of-X demultiplexor for increase number of available chip selects. For example you can use four GPIO pins and 74154 (4514) for generating sixteen CS signals...  

Spifd2 = fopen (spi1:2, NULL);

Spifd3 = fopen (spi1:4, NULL);

Spifd4 = fopen (spi1:8, NULL);

…

result = fwrite (buffer1, 1, 1, Spifd1);

/*Does it means the function will call the callback function "set_CS()"?Does it mean that I shoud set the CS0 as 0(select the chip) and the other signals as 1 in the  callback function "se_CS()"?*/

Yes, exactly.

result = fwrite (buffer2, 1, 1, Spifd2);

result = fwrite (buffer3, 1, 1, Spifd3);

result = fwrite (buffer4, 1, 1, Spifd4);

You typically call Spifd1 from different task than Spifd3, SPI driver is prepared for that situation and only one from SpifdX could be bus owner at the same time, others must wait until task executes fflush (SpifdX);.

3)

Yes, any call IO_IOCTL_FLUSH_OUTPUT (fflush (SpifdX);) or IO_IOCTL_SPI_FLUSH_DEASSERT_CS command or by closing the file handle with _io_close() (in this case it depends on who is currently owner of SPI bus) will call “set_CS” function.

/*Does it mean that fflush and _io_close() function will  set cs_mask as 0 and transfer it to the “set_CS” function and I should set all the signals as 1 in the function(de-asserted all the chips)?*/

Yes, exactly.

4)If the task call  fwrite (buffer2, 1, 1, Spifd2),does it mean that the ask should wait until the SPI completes the data transmission?

1. Yes. If you call fwrite (buffer1, 1, 1, Spifd1); and after that you call fwrite (buffer2, 1, 1, Spifd2);  Spifd2 must wait until Spifd1 finish his transfer and task call fflush (Spifd1). After that Spifd2 could send his data. So, correctly it should be:

result = fwrite (buffer1, 1, 1, Spifd1);

fflush (Spifd1);

result = fwrite (buffer2, 1, 1, Spifd2);

fflush (Spifd2);

result = fwrite (buffer3, 1, 1, Spifd3);

fflush (Spifd3);

result = fwrite (buffer4, 1, 1, Spifd4);

fflush (Spifd4);

Important is that it will work even when you call fwrite from different tasks.

Is there interrupt method for read and write SPI? For example,the task sleeps after calling fwrite and it wates up after the SPI completes the data transmission.

Yes, exactly. SPI uses interrupts therefore fwrite () will block current task until data transfer is finished and MCU could work on other tasks in meantime. The same is valid for fread,…

So, if you have three tasks and every task sends 200 bytes over the same SPI:

1. task1 call fwrite and it blocks task1 until transfer finish
2. task2 call also fwrite but SPI must wait until first write finish. So, it will blocks task2 until first transfer finish
3. task3 call also fwrite but SPI must wait until first write finish. So, it will blocks task3 until first transfer finish
4. idle task will run until first SPI transfer finish
5. when first SPI transfer finish, it will unblock task1 and when task1 call fflush, it will unblock second write to SPI….

5),How much data can the SPI master send out in the function "fwrite" one time?

This is not limited. It depends on your needs and available memory.

6),How much data can the SPI master buffer?

For example:

I send out the request data to the slaver and I read the response data 2ms later.And the slaver send out 200 bytes response in the 2ms.Can the SPI master  buffer the response data  if I do not read them immediately?

This is just misunderstanding. In case of SPI only master could generate clock, therefore you don’t need any buffer as in UART case. SPI works as “simple” shift registers. So, when you call fread for 200 bytes SPI module will start generate clock and read data from slave.

Size of data block isn’t limited. It depends on your needs and available memory – you have to allocate buffer where SPI will store received data.

[小勇邹]

Thank you very much.

6), How much data can the SPI master buffer?

For example:

I send out the request data to the slaver and I read the response
data 2ms later. And the slaver send out 200 bytes response in the 2ms.Can the
SPI master  buffer the response data  if I do not read them
immediately?

This is just misunderstanding. In case of SPI only master could
generate clock, therefore you don’t need any buffer as in UART case. SPI works
as “simple” shift registers. So, when you call fread for 200 bytes SPI module
will start generate clock and read data from slave.

Size of data block isn’t limited. It depends on your needs and
available memory – you have to allocate buffer where SPI will store received
data.

Yes, it is misunderstanding.

So does it mean that the slaver only response the data actually when the master start generate clock and read data from slave?

If the system works as a slaver and calls the function “fwrite”, the task will block until the master calls the
function “fread” and the communication finishes. Is it right?

If the master calls the function “fread” and the slaver does not response anything, the function “fread” also
will read some error data and the master will finish the communication. Is it right?

[RadekS]

Unfortunately I didn’t test SPI slave till now, but I am almost sure that you are right: If the system works as a slaver and calls the function “fwrite”, the task will be blocked until the master calls the function “fread” and the communication finishes.

Yes, if slave will not call fwrite and master calls the function “fread”, master will generate clock and master will probably real all bytes as 0xFF. Note: if master want read some data from slave, slave must write data prior master start read.

[RadekS]

1)

As it is written in MQX_IO_User_Guide.pdf, cs_mask will tell you how to set chip select pins.

So, if you open SPI1:1 and SPI1:8, cs_mask will give you one followed of numbers - 1,8 or 0 (it depends on type of even which causes calling set_CS()). 0 has special meaning and it means that you have to set all CS pins to inactive state (typically high level).

cs_mask doesn’t need to be directly mask, it could be any number. So, you can open SPI1:22 and when you write to this interface, cs_mask will contain number 22. Note: this is valid only for case when we use software callback.

2)

Yes, you should set all CS pins in “set_CS” function. set_CS() function is always just one. cs_mask will tell you how to set your CS pins. You don’t need modify the source code. You can do for example:

Spifd1 = fopen (spi1:1, NULL);

Spifd2 = fopen (spi1:2, NULL);

Spifd3 = fopen (spi1:4, NULL);

Spifd4 = fopen (spi1:8, NULL);

…

result = fwrite (buffer1, 1, 1, Spifd1);

result = fwrite (buffer2, 1, 1, Spifd2);

result = fwrite (buffer3, 1, 1, Spifd3);

result = fwrite (buffer4, 1, 1, Spifd4);

You typically call Spifd1 from different task than Spifd3, SPI driver is prepared for that situation and only one from SpifdX could be bus owner at the same time, others must wait until task executes fflush (SpifdX);.

3)

Yes, any call IO_IOCTL_FLUSH_OUTPUT (fflush (SpifdX);) or IO_IOCTL_SPI_FLUSH_DEASSERT_CS command or by closing the file handle with _io_close() (in this case it depends on who is currently owner of SPI bus) will call “set_CS” function.

Have a great day,
RadekS

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[小勇邹]

5),How much data can the SPI master send out in the function "fwrite" one time?

6),How much data can the SPI master buffer?

For example:

I send out the request data to the slaver and I read the response data 2ms later.And the slaver send out 200 bytes response in the 2ms.Can the SPI master  buffer the response data  if I do not read them immediately?