Can the i.MX6Q LVDS ouput be configured such that HSYNC, VSYNC, and DE signals are the high bits?

[camz]

We are using the DS90CF386 part to convert LVDS to parallel data which is then connected to parallel to TMDS bridge to eventually drive a DVI-D connector.

Just want to confirm that LVDS data bits can be configured such that we can properly connect the HSYNC, VSYNC, and DE signals, since the parallel to TMDS bridge part has dedicated pins for these signals.

Cheers,

Camz.

[jimmychan · Accepted solution]

I think you are talking about the bit mapping of LVDS, right?

LDB supports two mapping standards:

• SPWG mapping

• JEIDA mapping

[camz]

Correct, I am asking about the bit mapping.  This was the information I needed.  I was having a hard time finding this information in the i.MX6 reference manual (there is surprisingly little detail on the display and camera configurations).  Based on Igor's response though it seems that the i.MX6 and the i.MX53 share the same graphics setup, so now I at least know to look in the i.MX53 manual for details when I can't find them in the i.MX6 manual.

I can now work out the mappings through the various bridge parts to determine the proper connections.

Is there any reference or recommended design from Freescale for how to connect the LVDS ports to a DVI-D or HDMI connector instead of driving an LCD panel?

Cheers,

Camz.

[igorpadykov]

Hi Martin

I am afraid they can not be configured so, because IPU DI sync active levels

are low, depicted on IMX6DQCEC Figure 68. Interface Timing Diagram.

LDB module just translates IPU DI syncs, it can not change its polarity,

LDB-IPU connections are depicted in MX53UG Figure 18-1. Available Display Interfaces.

Probably for changing polarity one can reprogram timing generators,

Table 68. Video Signal Cross-Reference IMX6DQCEC shows hsync,vsync,drdy allocation.

Link below shows how to change microcode for generating sync signals

Re: i.MX53: How to move VGA external HSYNC and VSYNC signals to different pins?

Best regards

igor