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Unable to integrate a Marvell 88E6071 switch on imx28 board with MII/MDIO

Question asked by Oliver Graute on Nov 6, 2014
Latest reply on Dec 15, 2014 by Oliver Graute

We're currently trying to communicate using MII/MDIO bus from a IMX28 CPU to a Marvell Ethernet Switch (88E6071).

We also using MDC / MDIO link to configure it from a userspace tool called mii_diag. Here we can set registers of the switch manually.

The MDC / MDIO link works well. We can see when a connection is established on a port of the switch.

 

But now we are trying to use the Distributed Switch Architecture of the Marvel Switch via the MDIO Bus.

 

From the CPU point of view, this external(DSA) Marvell device needs to be driven to take switch configuration and commands.

So we need some sort of device driver to initialise and drive the DSA chip. We found the gianfar, fsl_pq_mdio drivers In Linux Kernel Sources.

Are these drivers the right on for IMX28 MDIO_BUS Support?

How to adapt the Device Tree for MDIO_BUS Support?

 

 

We using Linux 3.9.11  Environment with gianfar fsl_pq_mdio driver.

We are using this dts to configure our switch and mdio_bus :

 

 

mdio_bus: mdio {

        #address-cells = <1>;

        #size-cells = <0>;

     device_type = "mdio";

        compatible = "fsl,gianfar-mdio";

        status = "okay";

 

         ethphy0: ethernet-phy@0 {

                 reg = <0>;

         };

         ethphy1: ethernet-phy@1 {

                 reg = <1>;

                };

         };

}

   dsa@0 {

        compatible = "marvell,dsa";

        #address-cells = <2>;

        #size-cells = <0>;

 

 

        interrupts = <10>;

        dsa,ethernet = <&mac1>;

         dsa,mii-bus = <&ethphy1>;

 

 

        switch@0 {

            #address-cells = <1>;

            #size-cells = <0>;

            //reg = <16 0>;   /* MDIO address 16, switch 0 in tree */

            reg = <5 0>;   /* MDIO address 16, switch 0 in tree */

 

 

            port@0 {

                reg = <0>;

                label = "lan1";

                phy-handle = <&ethphy1>;

            };

 

 

            port@1 {

                reg = <1>;

                label = "lan2";

            };

 

 

            port@2 {

                reg = <2>;

                label = "lan3";

            };

 

 

            port@3 {

                reg = <3>;

                label = "lan4";

            };

 

 

            port@4 {

                reg = <4>;

                label = "lan5";

            };

 

 

            port@5 {

                reg = <5>;

                label = "cpu";

            };

 

 

        };

 

 

        };

    };

 

Nachricht geändert durch Oliver Graute

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