My company's products using PowerQUICC run on two different operating systems. The original code includes a number of the workarounds in AN3532 concerning Instruction Cache Parity Errors and others.
Our newer OS is based on Linux, and while I see that the kernel does include a few workarounds, these do not apply to the code for processors that we are running, and the code in the Linux kernel looks slightly different to what I would expect given the app note.
Specific questions:
The Linux change to which I refer is: powerpc/e500mc: Implement machine check handler. · fe04b11 · torvalds/linux · GitHub
Thanks
Tony
Solved! Go to Solution.
The errata CPU30, mentioned in the AN3532 appnote, is present only in rev 2.0 of the e500 core. This is quite old revision, it was used in old processors like MPC8541 mentioned in the tags of this topic.
Starting from core revision 3.0 (from MPC8572 processor), the errata CPU30 is not listed as present, so this means this is fixed in e500 core starting from revision 3.0
Regarding the machine check code - in case of machine check because of multibit error machine check handler may handle this error in different ways. The way, described in the errata is relatively complex - it requires cache inhibited region to place machine check handler and so on.
Invalidating whole cache is much easy and therefore more safe way. Of course, it takes more time, but assuming the procedure is not executed very frequently, I think performance impact may be ignored.
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The errata CPU30, mentioned in the AN3532 appnote, is present only in rev 2.0 of the e500 core. This is quite old revision, it was used in old processors like MPC8541 mentioned in the tags of this topic.
Starting from core revision 3.0 (from MPC8572 processor), the errata CPU30 is not listed as present, so this means this is fixed in e500 core starting from revision 3.0
Regarding the machine check code - in case of machine check because of multibit error machine check handler may handle this error in different ways. The way, described in the errata is relatively complex - it requires cache inhibited region to place machine check handler and so on.
Invalidating whole cache is much easy and therefore more safe way. Of course, it takes more time, but assuming the procedure is not executed very frequently, I think performance impact may be ignored.
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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