My company's products using PowerQUICC run on two different operating systems. The original code includes a number of the workarounds in AN3532 concerning Instruction Cache Parity Errors and others.
Our newer OS is based on Linux, and while I see that the kernel does include a few workarounds, these do not apply to the code for processors that we are running, and the code in the Linux kernel looks slightly different to what I would expect given the app note.
- Does the code introduced into Linux in 2010 directly relate to the application note AN3532?
- (my own answer) Algorithm in the application note just invalidates one cache line, the Linux code flushes the entire instruction cache. The app note algorithm also covers another case - not sure if this is required if the whole cache is flushed?
- Can we run this exact same code for the e500 case (the code in Linux is for e500mc)?
- (my own answer) There seem to be slight differences in the way the flush case bit works for e500 and e500mc, so the code would have to be changed slightly.
- Are there more up to date app notes relating to these issues?
- (my own answer) Couldn't find any in the archives.
- Are there existing patches that address these issues?
- Is Freescale interested in getting some of these workarounds into the main Linux project?
The Linux change to which I refer is: powerpc/e500mc: Implement machine check handler. · fe04b11 · torvalds/linux · GitHub