We are investigating the some phenomenon.
It's called the "white screen after power fluctuation test bug".
We tried to manually turn on/off power repeatedly in our lab, and we managed to reproduced the bug after about 2 hours of test. When the car kit screen becomes white screen, we measured the TW8836(LCD video processor:which is connected to i.MX6 LCD IF) dot clock and there is no signal on the clock line(we don't have high speed oscilloscope to measure the LDB clock). We guess this indicates that the LDB clock has stopped. If this is really the case, then we think at least the following reasons can make the LDB clock disappear: (1) the LDB clock source (PLL2 PFD0, ie. PLL_SYS PFD_528) has stopped; (2) the LDB has been disabled (3) the IPU DI has problem such that the LDB is starved to death.
For (2) it is unlikely since there is no decisive software logic can causing this randomly appearing phenomena;
For (3), we don't have any information about similar reported problems in the IPU driver in freescale BSP;
For (1) , We found that in the u-boot code provided by freescale BSP (u-boot-2009.08), there is a paragraph of description(\cpu\arm_cortexa8\mx6\generic.c, arch_cpu_init(), line 1102):
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
* to make sure PFD is working right, otherwise, PFDs may
* not output clock after reset, MX6DL and MX6SL have added 396M pfd
* workaround in ROM code, as bus clock need it
Would you please teach us what is the detail of this imx6 hardware limitation? Especially, in what operation condition this hardware limitation will cause PLL PFDs to stop outputting clock? And what is the software caution points in setting the PFD divisor?
FYI the code we used when setting the PLL2_PFD0 in uboot is like this:
/* PLL_SYS, PFD0 enable */
writel(0x80, ANATOP_BASE_ADDR + 0x104); // gate it at first
reg = readl(ANATOP_BASE_ADDR + 0x100);
reg &= ~0x0000003F;
reg |= 0x00000023;
writel(reg, ANATOP_BASE_ADDR + 0x100);
writel(0x80, ANATOP_BASE_ADDR + 0x108); // remove gating