I'm using a FRDM-KL26Z demo board, REV E and code mark MKL26Z128VLH4 / 1N15J / CTCTAB1340L.
I'm trying to configure the MCU into VLPS mode to achieve 2.8-7.8uA (as specified in the datasheet).
I'm using the example in the AN4503 - 8.1.9. Entering VLPS mode (page 24). I'm using the functions "enter_vlps()" and "deepsleep()". In my code, the CME0 bit is 0, the ALVP bit is 1 and the STOPM bits are b10. With this code the MCU current is 150uA, too far from the 2.8-7.8uA specified..
In the page 5 of the AN4503 (point 2.1.8. Very Low Power Stop mode) there is a sentence that says: "Expect IDD from 0.2 to 1 mA. Use of BLPE mode is recommended for VLPR and VLPS operation. See errata for more information.".
I've read the "Mask Set Errata for Mask 1N97F" the errata ID 5666 and says:
e5666: PMC: Maximum current consumption in VLPR, VLPW, VLPS, LLS and VLLS modes may be higher than data sheet specification.
Errata type: Errata
Description: Maximum current consumption in Very Low Power Run (VLPR), Very Low Power Wait (VLPW), Very Low Power Stop (VLPS), Low Leakage Stop (LLS) ,Very Low Leakage Stop3 (VLLS3) ,Very Low Leakage Stop2 (VLLS2) ,Very Low Leakage Stop1 (VLLS1) , and Very Low Leakage Stop0 (VLLS0) modes within an operating range of -40°C to 25°C may exceed data sheet specification.
Note: Some devices do not feature all of the power modes listed above. Refer to the
Reference Manual to determine if a particular low power mode is available on your device.
Workaround: If maximum current consumption in these low power modes exceed system requirements, a higher power mode should be used.
So I have a few questions:
1. Can this explain my consumption of 150uA in this mode??
2. What means exactly "Use of BLPE mode is recommended for VLPR and VLPS operation" in the page 5 of the AN4503? I'm using a BLPI, The internal reference 32.768KHz clock.
3. If I use an external 32KHz clock, the consumption will be the specified?
4. The code mark of the chip has this problem described in the errata?
Thanks for your help.