I am porting some code to the MX6SL and it uses critical sections to prevent clashes between ISR / Main shared memory. I would like to use the most effective mythology for implementing the functionality on the MX6 and try to use code from the SDK 1.1 if possible.
The existing code very simply reads CPSR to a local (stack) variable and then disables global interrupts. (this takes 2 ARM asm instructions). After the critical section a second macro restores the CPSR. This has worked well and I could probably do the same thing on the MX6 (cortex A9). However, I am now using the void IRQ_HDLR(void) provided by the SDK and it includes calls to the GIC which is new to me. I have read the Datasheet on it, but I was thinking that there may be some gotchas involved in disabling interrupts the way I was before and using this new IRQ_HDLR.
Specifically, I had a problem when I tried to call arm_set_interrupt_state(false) from an ISR. The code started executing functions in cortex_a9.s that I never called.
My question is:
Is there a "Critical Section" model that is compatible with the Bare metal SDK? Also, can I use the GIC to make Peripheral Specific Critical sections? or are the enable_interrupt(..)/disable_interrupt(..) GIC functions not suitable to be used in that way (maybe not thread safe/reenterant themselves) ?