I am using a PXS3020(473 pinout) controller for a project. I am trying to interface external memory through EBI.
I am using all the four chip selects and the details are given below.
1.) CS0 is connected to flash memory(2 MB) - No clock out, No burst memory access, 55 ns access time
2.) CS1 is connected to SRAM memory(4 MB) - No clock out, No burst memory access, 55 ns access time
3.) CS2 is connected to SRAM memory(4 MB) - No clock out, No burst memory access, 55 ns access time
4.) CS3 is connected to FPGA memory(256 KB)
The register configuration that I did is given below.
EBI_MCR - 0x0000_0005(No external master, 16 bit data port, using 16 to 31 as data line, No multiplexed address and data lines, 22 bit address(ADDR10 to ADDR31))
EBI_BR0 - 0x2000_0803;
EBI_OR0 - 0xFFE0_0060;// 6 wait states
EBI_BR1 - 0x2020_0803;
EBI_OR1 - 0xFFA0_0060;
EBI_BR2 - 0x2060_0803;
EBI_OR2 - 0xFF60_0060;
EBI_BR3 - 0x20A0_0803;
EBI_OR3 - 0xFF5C_0060;
Output buffer enable(OBE) bit is enabled for all the EBI output signals, except Data lines in PCR registers.
After this configuration, I tried to access Address 0x20001000. But I could not read or write.
I probed the the CS0 signal and found that no chip select signal is generated by the EBI.
I am using 90 MHz system clock. I could not find any EBI module clock divider register in PXS3020 reference manual Rev.1.
I am not dividing the system clock since no register is given for EBI clock divider values(Not available in PXS3020 reference manual Rev.1).
Kindly help me to find the problem with the configuration.
Also I have the following queries.
1.) Are PXS3020 and MPC5675K register details same(Are PXS3020 and MPC5675K compatible?)?
2.) I created the project using CW eclipse IDE 10.4 and controller was selected as MPC5675K instead of PXS3020. Will it create any problem?
3.) How to configure EBI Clockout for slower speed(Please give the register address)?
4.) Are PCR register for EBI signal to be configured for week pull up?(I am not able to write in to the field)
5.) In section,EBI external calibration clock divider, it is given that devier value is 6 least significant bits,
but in register detail it is given as 6 most significant bits(Refered MPC5675K reference manuual Rev.10).