I'm trying to configure the DDR interface in a Kinetis K61 but I'm struggling with the correct settings for the DDR_PAD_CTRL register.
How should one chose correct settings for the SPARE_DLY_CTRL bits? The documentation (reference manual K61P256M150SF3RM rev 2) doesn't explain how the buffers correlate with the behavior of the DDR PHY.
What is delay chain #0?
What is spare logic?
What are buffers?
It is also confusing to see that the reset value for the reserved bits [8:15] are set to 0x2 when the documentation says "This read-only field is reserved and always has the value zero." This is obviously not the case as I can read a value != 0 after reset.
All in all this register lacks documentation needed to understand how it should be used.
Our setup is in all aspects identical with the TWR-K70F120M board and in the code examples we can find the SPARE_DLY_CTRL is configured to "10 buffers", why is that?