Hey Nick,
Yeah my original thought was that the DAC registers were synchronized but after reading the manual I know that they are not. (Some registers only affect the actual hardware once a specific register is written to.)
Also the addresse (4003F000) is correct because the offset is added to in case of DATH.
The problem with the PE implementation is just that it takes ages to run. basically there is a long delay between the first write and the second.
You can speed up the proccess but you will loose some of the comfort of reusability and generality.
What the original macro does is:
write the low byte to the low register
read the high register
keep the "reserved" bits intact and add the new high byte
write the high register
This assumes that freescale could at some point use the reserved bits for some other purpose and this code leaves them unaffected.
But this will probably never happen.
Try this definition and report if the spikes have changed:
#define DAC_PDD_SetData(PeripheralBase, Data, RegIndex) ( \
(DAC_DATH_REG(PeripheralBase,(RegIndex)) = \
(uint8_t)((uint16_t)(Data) >> 8U)), \
(DAC_DATL_REG(PeripheralBase,(RegIndex)) = \
(uint8_t)(Data)) \
)
Martin