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Configuring the clock for PIT

Question asked by Yves B on Feb 28, 2014
Latest reply on Mar 3, 2014 by Mark Butcher

Hi,

 

I'm still discovering the K20 chip using the Tower K20 demo kit with the demo_gpio project supplied by freescale.

I have set a PIT as described in this earlier topic: https://community.freescale.com/thread/320172

 

I've left all the MCG config as is in the demo project.

the maximum tick frequency I can get with the PIT is around 2MHz, although the mcg_clk_hz is 72.000.000 (= core_clk)

 

Is this normal? I thought the max freq achievable with PIT should be half the core clock.

 

regards,

Yves B

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