I am attempting to integrate a PCIe peripheral configured as an EP with the mx6 configured as a RC. Initial configuration goes well, and the device is able to read/write into the mx6's memory space once it has been granted bus mastering. Unfortunately the device has been unable to trigger an ARM interrupt when signaling a MSI.
The EP has had its MSI's enabled and allocated (8 of them EP 0, MSI 0-7), both the MX6 and EP share the same MSIC address, the MSIC enable bits are set and the MSIC mask is cleared. An interrupt handler is attached to IRQ 152.
My program dumps the MSIC mask and status before and after the test:
0[0x1ffc82c 0x1ffc830]:current mask:0x0 status:0x0
<EP writes MSI>
0[0x1ffc82c 0x1ffc830]:current mask:0x0 status:0x1
At this point no ARM interrupt is triggered, despite the fact that the status bit is asserted.
I've manually inspected the ARM GIC and confirmed that IRQ 152's ISENABLERn bit is asserted. To test my ISR routine I've manually set the ISPENDRn register and successfully triggered the handler.
What could cause an asserted MSI status bit to not trigger the ARM GIC?
Is there a way to check the state of msi_ctrl_int ?