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SPI Fram interface timing

Question asked by Doug Paulsen on Nov 26, 2013
Latest reply on Nov 27, 2013 by TomE

I'm sure this has been dealt with before, but here's a SPI question.  I'm working interfacing an MCF51AC micro to a Ramtron FRAM.  The fram requires multi-byte commands separated by a de-activated /CS.  You can tell when a tx byte has cleared the tx buffer, but how do you know when the byte has cleared the shift register and the /CS line has gone inactive?  It is only then when the fram will properly accept the next command sequence.  At this point, it looks like one must just wait an fixed delay for the SPI subsystem to finish.  I'm not keen to writing such software timing loop dependent code.  Is there any other way to know an SPI tx is truly done?  Thanks for any thoughts!