I have question of Vybrid ldrex/strex operations.
In the case of First access of STREX By CA5,It became the result of the following figure.
May be,does VyBrid not support STREX/LDREX between CA5 and CM4?
I'm not sure I fully understand all the details of the above, but the general issue is with handling shared resources between the two cores I believe.
The Vybrid architecture is completely open with that regard so no hardware protection exists, it is entirely up to software to be designed and protected from this type of issue, the SEMA4 module is intended to aid with this, so for example if memory is not in use, as indicated by the SEMA4 register (which itself has no dedicated function, software left to define it's operation), the first core to attempt to access the memory should flag the memory as locked out in using the SEMA4, perform the LDREX/STREX and then clear the SEMA4, the other core should check the SEMA4 before attempting to access the memory.
There is no global lock monitor in the system. The cortex-A5 will have a local lock monitor, so the strex/ldrex can be used to implement lock-free code on the A5 CPU only. This can be used with TrustZone, as long as the monitor code does an clrex on world switches. See ARM synchronization primitives on an MPCore and Arm synchronization primitives (PDF). So a secure/normal world lock-free algorithm should be usable on a Vybrid, but the M4 CPU does not support the global monitor/AXI signals that would be needed to have multi-core lock-free code. This is the reason for the SEMA4 module; otherwise why not do just exactly what you propose.
Hth you Soichi.
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