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VDD_ANA_PLL gets disabled when leaving Boundary Scan EXTEST state

Question asked by Robert Humphrey on Sep 13, 2013
Latest reply on Sep 17, 2013 by Yuri Muhin

We have a board using an i.MX536 with LTC3589-1 PMIC, for which we are developing boundary scan tests.  The JTAG_MOD pin is high, and we are able to communicate with the device, taking it via SAMPLE into EXTEST where we can run all of our tests without problems.

 

However, when the testing stops the device enters a state where it is no longer possible to communicate with it via JTAG.

 

The problem appears to be related to the internal VDD_ANA_PLL regulator getting disabled, which is also connected to NVCC_CKIH and NVCC_RESET.  The VDD_REG supply remains stable at the point when VDD_ANA_PLL turns off, but this change in VDD_ANA_PLL then disables a number of the other rails.

 

The disabling of VDD_ANA_PLL appears to occur at the point when the device leaves EXTEST.  Leaving EXTEST by selecting a different instruction, transitioning the TAP state machine through to test-logic-reset or asserting nTRST all appear to have the same effect.

 

We can't find any explanation why this might be happening, because power-cycling the board resolves the problem, so what might be temporarily disabling VDD_ANA_PLL?  Furthermore, how can we stop it happening or at least recover from the situation without needing to power cycle the board?

 

Thanks,

Rob

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