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setting divider for mmdc_ch1_axi_clk

Question asked by simonbraunschmidt on Jun 28, 2013
Latest reply on Jul 1, 2013 by Anson Huang

Hi

 

I have troubles setting up the LVDS pixel clock to frequencies below 38.79 Mhz, compare also the discussion in "LVDS pixel clock on i.MX6" [1].

 

To allow lower frequencies, I came up with the idea to derive the LDB clock from mmdc_ch1_axi_clk and in turn derive mmdc_ch1_axi_clk from

pll2_pfd_352M (PLL2,PFD2).

mmdc_ch1_axi_clk itself does not seem to be used by other modules in the kernel 3.0.35_4.0.0, and the current setup is to derive the clock from pll2_pfd_352M directly, so this seems possible.

This would allow to use both the divider for mmdc_ch1_axi_clk (/1 .. /8) and the PFD to generate the clock.

 

Example:

to generate a clock near 33.26 MHz as needed in [1], pll2_pfd_352M is set to 475.2 MHz and the divider for mmdc_ch1_axi_clk is set to 2. We thus obtain

475200000/2 MHz ^= LVDS bitrate 237.6 Mbit/s

237.6 MHz/7 ^= LVDS Pixelclock 33.94 MHz

 

The Problem:

I have everything set up already in code, to reparent the mmdc_ch1_axi_clk and to derive the nearest clock frequency by combining the divider and the PFD. As per the manual, after changing the bits at MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (the divider), you have to wait for MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY to toggle to zero again, compare "18.5.1.5.6 Divider change handshake" .

 

I used the following code to wait for the bit, but it never toggles to zero.

 

        if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
             & MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY), SPIN_DELAY))
                panic("_clk_mmdc_ch1_axi_set_parent failed\n");

 

I also tried other kinds of delay-loops, I can see that the bit does not toggle to zero for as long as 3 seconds.

 

But when I disable the handshaking,

 

       reg = __raw_readl(MXC_CCM_CCDR);
       reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
       __raw_writel(reg,MXC_CCM_CCDR);

 

the WAIT(condition,delay)-loop above succeeds (it looks like the bit is then not ever set to indicate "wait-for-handshake"), and I can even observe the desired clock on LVDS, as I checked with a scope.

 

My 3 questions:

Can you help me understand why the handshake obviously does not finish?

Do the module or modules that derive their clock from mmdc_ch1_axi_clk have to be in a specific condition before attempting to change to divider, so that the handshake can succeed?

Would it be OK to just delay for some amount of time (how long typically?), instead of waiting for the handshake-indication?

 

related discussion:

[1] LVDS pixel clock on i.MX6

     https://community.freescale.com/message/331739


Best Regards,

Simon Braunschmidt

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