Looking at the bootloader sample code, i have some doubt. I am using it with a FRDM-KL05Z and the KL05 has one flash block. The reference document says we cannot execute from a block and write to the same block at the same time (27.4.5 Flash Reads and Ignored Writes). Trying that would cause a read collision error (RDCOLERR). But exactly that happens in the sample code and it works, except i don't understand why. The sample code mentions "copy code to RAM" but doesn't do it. The procedure Command_Lanuch() is executed from flash, which appears to be out of specs.
Does it happen to work because of cache memory?
Is this guaranteed to work (once interrupts are disabled)? What other conditions to observe?
This situation appears similar to setting the NVIC table base pointer. According to ARM Cortex M0+ documents that operation should be followed by a cache barrier instruction that i have never seen in Freescale samples.