Does anyone have experience accessing the IPU registers directly using a JTAG debug tool? I need to verify that the settings being passed to the CSI configuration registers are correct.
The addresses in the RM aren't making sense to me. Using a Lauterbach debugger I expect to be able to access the IPU registers directly when the processor is taken out of reset before enabling the MMU (e.g., stopped in u-boot). Bus Errors occur when using the addresses in the RM Memory map and also when using values contained in plat_mxc/include/mach/mx6.h. It should be noted that the memory maps in the RM appear to have a discontinuity between sections 2 & 39.
It appears the addresses in the perimx6.per file provided by FSL point to the middle of DDR (0x20400000), so they are useless.