Is the way to do this directly in the PRM file.
Code:
/*****************************************************************************
ResetVectorTable
Interrupt vector table for S12XDP512
This is the default CPU interrupt vector table at reset: IVBR = $FF
Other vector tables can be created and used by changing IVBR
*****************************************************************************/
const tIsrFunc ResetVectorTable[] @0xFF10 =
{
SpuriousISR, /* 0xFF10 Spurious Interrupt */
ReservedISR, /* 0xFF12 Reserved */
ReservedISR, /* 0xFF14 Reserved */
ReservedISR, /* 0xFF16 Reserved */
ReservedISR, /* 0xFF18 Reserved */
ReservedISR, /* 0xFF1A Reserved */
ReservedISR, /* 0xFF1C Reserved */
ReservedISR, /* 0xFF1E Reserved */
ReservedISR, /* 0xFF20 Reserved */
ReservedISR, /* 0xFF22 Reserved */
ReservedISR, /* 0xFF24 Reserved */
ReservedISR, /* 0xFF26 Reserved */
ReservedISR, /* 0xFF28 Reserved */
ReservedISR, /* 0xFF2A Reserved */
ReservedISR, /* 0xFF2C Reserved */
ReservedISR, /* 0xFF2E Reserved */
ReservedISR, /* 0xFF30 Reserved */
ReservedISR, /* 0xFF32 Reserved */
ReservedISR, /* 0xFF34 Reserved */
ReservedISR, /* 0xFF36 Reserved */
ReservedISR, /* 0xFF38 Reserved */
ReservedISR, /* 0xFF3A Reserved */
ReservedISR, /* 0xFF3C Reserved */
ReservedISR, /* 0xFF3E Reserved */
ReservedISR, /* 0xFF40 Reserved */
ReservedISR, /* 0xFF42 Reserved */
ReservedISR, /* 0xFF44 Reserved */
ReservedISR, /* 0xFF46 Reserved */
ReservedISR, /* 0xFF48 Reserved */
ReservedISR, /* 0xFF4A Reserved */
ReservedISR, /* 0xFF4C Reserved */
ReservedISR, /* 0xFF4E Reserved */
ReservedISR, /* 0xFF50 Reserved */
ReservedISR, /* 0xFF52 Reserved */
ReservedISR, /* 0xFF54 Reserved */
ReservedISR, /* 0xFF56 Reserved */
ReservedISR, /* 0xFF58 Reserved */
ReservedISR, /* 0xFF5A Reserved */
ReservedISR, /* 0xFF5C Reserved */
ReservedISR, /* 0xFF5E Reserved */
UnimplementedISR, /* 0xFF60 XSRAM20K Access Violation */
UnimplementedISR, /* 0xFF62 XGATE Software Error */
UnimplementedISR, /* 0xFF64 XGATE Software Trigger 7 */
UnimplementedISR, /* 0xFF66 XGATE Software Trigger 6 */
UnimplementedISR, /* 0xFF68 XGATE Software Trigger 5 */
UnimplementedISR, /* 0xFF6A XGATE Software Trigger 4 */
UnimplementedISR, /* 0xFF6C XGATE Software Trigger 3 */
UnimplementedISR, /* 0xFF6E XGATE Software Trigger 2 */
UnimplementedISR, /* 0xFF70 XGATE Software Trigger 1 */
UnimplementedISR, /* 0xFF72 XGATE Software Trigger 0 */
UnimplementedISR, /* 0xFF74 Periodic Interrupt Timer */
UnimplementedISR, /* 0xFF76 Periodic Interrupt Timer */
UnimplementedISR, /* 0xFF78 Periodic Interrupt Timer */
UnimplementedISR, /* 0xFF7A Periodic Interrupt Timer */
UnimplementedISR, /* 0xFF7C Reserved */
UnimplementedISR, /* 0xFF7E API Autonomous Periodical Interrupt */
UnimplementedISR, /* 0xFF80 LVI Low Voltage Interrupt */
UnimplementedISR, /* 0xFF82 IIC1 */
UnimplementedISR, /* 0xFF84 SCI5 */
UnimplementedISR, /* 0xFF86 SCI4 */
UnimplementedISR, /* 0xFF88 SCI3 */
UnimplementedISR, /* 0xFF8A SCI2 */
UnimplementedISR, /* 0xFF8C PWM Emergency Shutdown */
UnimplementedISR, /* 0xFF8E Port P Interrupt */
UnimplementedISR, /* 0xFF90 MSCAN 4 transmit */
UnimplementedISR, /* 0xFF92 MSCAN 4 receive */
UnimplementedISR, /* 0xFF94 MSCAN 4 errors */
UnimplementedISR, /* 0xFF96 MSCAN 4 wake-up */
UnimplementedISR, /* 0xFF98 MSCAN 3 transmit */
UnimplementedISR, /* 0xFF9A MSCAN 3 receive */
UnimplementedISR, /* 0xFF9C MSCAN 3 errors */
UnimplementedISR, /* 0xFF9E MSCAN 3 wake-up */
UnimplementedISR, /* 0xFFA0 MSCAN 2 transmit */
UnimplementedISR, /* 0xFFA2 MSCAN 2 receive */
UnimplementedISR, /* 0xFFA4 MSCAN 2 errors */
UnimplementedISR, /* 0xFFA6 MSCAN 2 wake-up */
UnimplementedISR, /* 0xFFA8 MSCAN 1 transmit */
UnimplementedISR, /* 0xFFAA MSCAN 1 receive */
UnimplementedISR, /* 0xFFAC MSCAN 1 errors */
UnimplementedISR, /* 0xFFAE MSCAN 1 wake-up */
UnimplementedISR, /* 0xFFB0 MSCAN 0 transmit */
UnimplementedISR, /* 0xFFB2 MSCAN 0 receive */
UnimplementedISR, /* 0xFFB4 MSCAN 0 errors */
UnimplementedISR, /* 0xFFB6 MSCAN 0 wake-up */
UnimplementedISR, /* 0xFFB8 Flash */
UnimplementedISR, /* 0xFFBA EEPROM */
UnimplementedISR, /* 0xFFBC SPI2 */
UnimplementedISR, /* 0xFFBE SPI1 */
UnimplementedISR, /* 0xFFC0 IIC0 */
UnimplementedISR, /* 0xFFC2 Reserved */
UnimplementedISR, /* 0xFFC4 CRG Self Clock Mode */
UnimplementedISR, /* 0xFFC6 CRG PLL lock */
UnimplementedISR, /* 0xFFC8 Pulse accumulator B overflow */
UnimplementedISR, /* 0xFFCA Modulus Down Counter Underflow */
UnimplementedISR, /* 0xFFCC Port H */
UnimplementedISR, /* 0xFFCE Port J */
UnimplementedISR, /* 0xFFD0 ATD1 */
UnimplementedISR, /* 0xFFD2 ATD0 */
UnimplementedISR, /* 0xFFD4 SCI1 */
UnimplementedISR, /* 0xFFD6 SCI0 */
UnimplementedISR, /* 0xFFD8 SPI0 */
UnimplementedISR, /* 0xFFDA Pulse accumulator input edge */
UnimplementedISR, /* 0xFFDC Pulse accumulator A overflow */
UnimplementedISR, /* 0xFFDE Enhanced Capture Timer overflow */
UnimplementedISR, /* 0xFFE0 Enhanced Capture Timer channel 7 */
UnimplementedISR, /* 0xFFE2 Enhanced Capture Timer channel 6 */
UnimplementedISR, /* 0xFFE4 Enhanced Capture Timer channel 5 */
UnimplementedISR, /* 0xFFE6 Enhanced Capture Timer channel 4 */
UnimplementedISR, /* 0xFFE8 Enhanced Capture Timer channel 3 */
UnimplementedISR, /* 0xFFEA Enhanced Capture Timer channel 2 */
UnimplementedISR, /* 0xFFEC Enhanced Capture Timer channel 1 */
UnimplementedISR, /* 0xFFEE Enhanced Capture Timer channel 0 */
UnimplementedISR, /* 0xFFF0 Real Time Interrupt */
UnimplementedISR, /* 0xFFF2 IRQ */
UnimplementedISR, /* 0xFFF4 XIRQ */
UnimplementedISR, /* 0xFFF6 SWI */
UnimplementedISR, /* 0xFFF8 Unimplemented instruction trap */
UnimplementedISR, /* 0xFFFA COP failure reset */
UnimplementedISR, /* 0xFFFC Clock monitor fail reset */
_Startup /* 0xFFFE Reset vector */
};
Alban.