Emmanuel Owusu

Read initial contents of L1/L2 and Tightly Coupled Memory cache on iMX53

Discussion created by Emmanuel Owusu on Mar 5, 2012

I want to access the initial contents of L1/L2 cache and the Tightly Coupled Memory (TCM) units on power-up of the iMX53.

 

I did some digging around in the ARM Cortex-A8 documentation and it appears that at least the processor has support for this. By default the hardware clears the valid bits for both L1 data cache and L2 unified cache. However, resetting of the L1 and L2 data cache can be controlled by the L1RSTDISABLE and L2RSTDISABLE pins, respectively (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Cihcbcgi.html). 

 

I cannot find a reference to the L1RSTDISABLE/L2RSTDISABLE reset pins in the Freescale literature (perhaps they are called something else or not supported on the iMX53). Does anyone know if ability to (1) disable cache clearing and (2) read the initial contents of the TCM/L1/L2 memory is supported on the I.MX53? I would appreciate any insights on this matter.

Outcomes