Hello Hasan,
The following code should demonstrate the technique of writing a single byte, and reading a single byte from the EEPROM. The EEPROM device is capable of writing and reading multiple byte sequences, but this would require additional buffers to be used.
Regards,
Mac
; RAM usage:
EEADDR EQU RAM ; Word register for EEPROM address
; EEPROM op-codes:
WRSR EQU 1 ; Write status register
WRITE EQU 2 ; Write EEPROM
READ EQU 3 ; Read EEPROM
WRDI EQU 4 ; Write disable
RDSR EQU 5 ; Read status register
WREN EQU 6 ; Write enable
; SPI settings:
SPIC1VAL EQU %01011100 ; SPI master, no interrupts,
; CPOL=1, CPHA=1
SPIC2VAL EQU $00
SPIBDVAL EQU $00 ; SPI_CLK divisor = 2
SS EQU 5 ; /SS output signal at PTB5
***************************************************************
* INITIALISE SPI
***************************************************************
SPI_INIT: MOV #SPIC1VAL,SPIC1
MOV #SPIC2VAL,SPIC2
MOV #SPIBDVAL,SPIBR
BSET SS,PTB ; Initial state is high
BSET SS,DDRB ; Set /SS for output
RTS
***************************************************************
* SPI TRANSACTION
* On entry, ACC = send byte value (SPISND only)
* On exit, ACC = returned byte value, and
* CF = 1 if OK, otherwise CF = 0 if timeout
***************************************************************
SPIRX: ; Receive byte from SPI
CLRA
SPISND: ; Send byte to SPI
STA SPID
; Wait for SPI Send/Rx
LDA #10 ; Timeout period 100 cycles
ST1: BRSET SPIRF,SPIS,ST2 ; Exit if SPI send complete
NOP
DBNZA ST1 ; Loop if not timeout
CLC
ST2: LDA SPID ; Also clears flag
RTS
***************************************************************
* WRITE BYTE TO EEPROM
* On entry, word register EEADDR contains EEPROM address,
* ACC = byte value to be written
* On exit, CF = 1 if OK, or CF = 0 if timeout
***************************************************************
EEWRITE: PSHA ; Save byte value to be written
BCLR SS,PTB ; Set /SS active
LDA #WREN ; Write enable op-code
JSR SPISND ; Send byte to SPI
BCC EW2 ; Exit if timeout
BSET SS,PTB ; Set /SS inactive
BCLR SS,PTB ; Set /SS active
LDA #WRITE ; Write op-code
JSR SPISND ; Send byte to SPI
BCC EW2 ; Exit if timeout
LDA EEADDR ; High address byte
JSR SPISND ; Send byte to SPI
BCC EW2 ; Exit if timeout
LDA EEADDR+1 : Low address byte
JSR SPISND ; Send byte to SPI
BCC EW2 ; Exit if timeout
PULA
JSR SPISND ; Send byte to SPI
BCC EW3 ; Exit if timeout
BSET SS,PTB ; Set /SS inactive
; Wait for write complete (maximum 10ms delay)
STA SRS ; Clear COP timer
EW1: BCLR SS,PTB ; Set /SS active
LDA #RDSR ; Read status register op-code
JSR SPISND ; Send byte to SPI
BCC EW3 ; Exit if timeout
BSET SS,PTB ; Set /SS inactive
AND #$01 ; Test RDY bit
BNE EW1 ; Loop if not ready
RTS
EW2: ; Timeout error occurred
PULA ; Adjust stack
EW3: BSET SS,PTB ; Set /SS inactive
RTS
***************************************************************
* READ BYTE FROM EEPROM
* On entry, word register EEADDR contains EEPROM address
* On exit, ACC = byte value, CF = 1 if OK, or CF = 0 if timeout
***************************************************************
EEREAD: BCLR SS,PTB ; Set /SS active
LDA #READ ; Read op-code
JSR SPISND ; Send byte to SPI
BCC ER1 ; Exit if timeout
LDA EEADDR ; High address byte
JSR SPISND ; Send byte to SPI
BCC ER1 ; Exit if timeout
LDA EEADDR+1 : Low address byte
JSR SPISND ; Send byte to SPI
BCC ER1 ; Exit if timeout
JSR SPIRX ; Receive byte from SPI
ER1: BSET SS,PTB ; Set /SS inactive
RTS
Message Edited by bigmac on 2006-09-22 01:26 PM
