[This is an udpate of the post http://forums.freescale.com/freescale/board/message?board.id=CFCOMM&message.id=236&query.id=985#M236]
I have returned to the subject because of the need to set a different divide value before the PLL input.
Unfortunately I still have the problem that the device is not responding to changes of the prescaler (MCF_CLOCK_CCHR).
To be sure that I am not changing the registers incorrectly I have added a memory dump of the first 16 bytes in the clock module peripheral space. This has confirmed that the MCF_CLOCK_CCHR value is defaulting to 4 (divide by 5) and then my code is setting it to 3 (divide by 4). This is performed with disabled PLL and the SYNCR register is each time afterwards written with a multiplication factor of x9 (div. 2 *18).
The PLL output is constantly 45MHz, irrespective of whether CCGR is set to 2, 3, 4 or 5.
This gives the impressions that the register can be written and read but the divide is fixed to 5.
Here are register details after booting and not attempting to set CCGR (all addresses are (byte) dumped incl. non-used, starting at IPSBAR + 0x12000).
0x71 0x07 0x38 0x00 0x01 0x94 0x00 0x00 0x04 0x00 0x00 0xf0 0x01 0x7d 0x78 0x40
The value 0x04 is seen at (IPSBAR + 0x120008) and the PLL output frequency is 45.0MHz. The status register shows that the PLL is locked, etc.
Here is the dump when CCGR is set to 0x03
0x71 0x07 0x38 0x00 0x01 0x94 0x00 0x00 0x03 0x00 0x00 0xf0 0x01 0x7d 0x78 0x40
It shows that the correct location has been modified and the PLL is locked. Still the PLL output frequency remains at 45.0MHz
If I set 0x08 to CCGR it reads back 0x00 (since only the lowest 3 bits can be written to), confirming again that the register is really being set correctly.
Please could you inform me whether this is a problem with the device or whether there is some special handling required to get the register value to be accepted for the prescaling?
Many thanks in advance.