James Botte

RS08 Reset, Interrupt, and ICS behaviour

Discussion created by James Botte on Jun 13, 2006
Latest reply on Nov 3, 2009 by Nataraja Badekila
I have four questions that don't seem to be answered in the data sheets or any of the application sheets I have found:

1. When I set the SOPT_RSTPE to 1 (enable), if the RESET* pin is low, will the chip go into RESET mode until the pin comes high again? This is the behaviour I would expect, and am hoping for.

2. If an interrupt is pending when a WAIT command is executed, will the WAIT immediately exit? Again, this is the behaviour I'd expect, and am hoping for.

3. If I set the trim registers immediately after coming out of POR or any other RESET, do I have to wait for the full 1ms before I can set BDIV to 0 (divide bus clock by one) or is it safe to set it right after I've set the trim? The code example in the MTIM app note (in RS08QRUG) seems to imply that it's okay, but there's a note in the data sheet that states that "The BDIV is reset to a divide by 2 to prevent the bus frequency from exceeding the maximum. The user should trim the device to an allowable frequency before changing BDIV to a divide by 1 operation." The timing in the back also implies that it is possible for an untrimmed clock to exceed the 10MHz internal bus speed maximum (21.33MHz/2), and the data sheet further states that "When changing from FBILP to either FEI or FBI, or anytime the trim value is written, the user should wait the FLL acquisition time, t_acquire, before FLL will be guaranteed to be at desired frequency."

4. Do the parts ship from Freescale with the correct trim values for that specific chip in memory locations $3FFA and $3FFB?

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