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Instruction Cache, MCF523x processor, CodeWarriors V10.0

Question asked by Dan Wermers on Nov 29, 2011
Latest reply on Dec 6, 2011 by Dan Wermers

Hello!    Please Help!


I have my own prototype design up and working.  Now I'm trying to get the cache enabled to increase performance.  For this processor, the cache is 8KBytes.  The processor also has a 64KByte internal SRAM (non-cachable).  Code is executed from an external Flash memory chip (8MBytes Flash on CS0 in x16 configuration).  The cache for this processor can either be instruction, data, or split 50%/50% instruction and data.  For my application, instruction only will provide best performance increase.


There are only three relevant registers to configure:  CACR, ACR0, ACR1.  Good to this point.  I want a single unified instruction cache, from the 8MBytes on CS0.  Thus I'd think that I would set ACR0 and ACR1 to the same value.  However, the documentation is vague on how best to set these registers such that they would both work in conjunction in the same base memory area.  In other words, the address space for ACR0 and ACR1 overlap completely.  Is this a problem?  I don't want something strange happening such as half of the cache being wasted because the cached instructions in both halves of the cache are the exact same. 


Each ACRx register covers an address area of 16 MBytes in size (i.e., A31:A24 must match the value in ACRx to be recognized as cacheable).  I could do something strange, such as memory map the Flash on CS0 across a boundary that is say, 4 MBytes.  That would allow me to split half of the memory into ACR0 and half into ACR1.  However, in reality, the total size of the executable code is going to be less than 512 KBytes (maybe even less than 256 KBytes).  It will be impossible to split that across non-overlapping 16 MByte boundaries.


If setting ACR0 and ACR1 the same results in wasting 1/2 of the cache, I'd rather use the cache as a 50% instruction, 50% data cache, with the data residing elsewhere, such as my external SRAM.  Though I have to be careful about that as there are DMA processes going on in this SRAM, and that is incompatible with caching.


I investigated a little further using the ColdFire Init utility.  It gives me a warning "The cache memory regions defined by ACR0 and ACR1 overlap, which may not be what you intended".


Any insight or documentation you can point me to would be appreciated greatly!