i.MXRT 106x FlexRAM power control

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i.MXRT 106x FlexRAM power control

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Sauli
Contributor I

iMXRT1064 RM says about the FlexRAM (among other things):

- 8 out of the 16 RAM banks (bank8 to bank15) can be powered off dynamically.
- Bank8~15 can be disabled with hardware fuse setting. When the fuse is set, total
  RAM size will be limit to 256 KB
- FLEXRAM has input fuse control signal to control ocram bank8~bank15 interface
  access. When the fuse bit is programmed, bank8~bank15 can't be accessed again and can
  be power down.

However, i cannot find any information what fuse that might be. There is a fuse setting to divide the 512k between ITCM, DTCM and OCRAM, but all available options add up to 512k, and I cannot find any other related fuse. Also, in the IOMUXC_GPR_GPR17 register you can select a bank to be 'not used', but that can be applied to all 16 banks, not just banks 8-15. Therefore that is unlikely to control bank power. So, does anybody know how banks 8-15 are powered off?

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Pavel_Hernandez
NXP TechSupport
NXP TechSupport

Hello, I'm Pavel and I will be supporting your case, I reviewed your information and determine the next app note could help you, please review the next links.

AN12077: Using the i.MX RT FlexRAM – Application Note (nxp.com)
How to use i.MX RT Low Power Feature (nxp.com)

Let me know if you have more questions,

Best regards,
Pavel

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744 Views
Sauli
Contributor I

AN12077 says that all iMXRT1064 FlexRAM banks are in the same power domain PDRAM0. 

 

AN12085 advices how to use PGC->MEGA_CTRL  to power off FlexRAM blocks on iMXRT1050.  iMXRT1064 only allows turning on/off the power for the whole FlexRAM. Yet the reference manual claims that blocks 8-15 can be powered off dynamically.

So no definite answer yet.

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Pavel_Hernandez
NXP TechSupport
NXP TechSupport

Hello, 

Sorry, I did not notice that, I did a report to get more details about that line in the RM.

Best regards,
Pavel

 

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Pavel_Hernandez
NXP TechSupport
NXP TechSupport

Hello,

As mentioned in AN12077, in RT106x all Flex RAM banks are assigned to the one power domain. So, RM is not perfectly correct, OCRAM2 can be divided into PDRET (64kB) and PDRAM1 448KB.

Best regards,
Pavel

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