What happens to WDOG1 if the Core loses its clock?

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What happens to WDOG1 if the Core loses its clock?

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mitterha
Senior Contributor I

Hello,

we would like to write an error message into flash after the watchdog fires an interrupt.

The Real Time Watchdog offers a backup reset functionality but the time after the interrupt is limited to 255 cycles of the bus clock.

1. Is it really limited to the bus clock? Is the bus clock the ipg_clk_root? If ipg_clk_root is 99 MHz this would mean that there are only 2,58 us which is too short for writing into flash.

The WDOG1 peripheral does not provide a backup reset description. Assume it is clocked from 32kHz LPO.

2. If the Core clock stops will the WDOG1 interrupt still be fired and will the WDOG1 peripheral reset the system after timeout? Or does the WDOG1 not work anymore after the Core clock is stopped?

Kind regards,

Stefan

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi Stefan,

 

I am sorry for the late reply. When handling interrupts it is always recommended to keep the handler as short as possible. Therefore is not recommended to write into flash inside IRQ.

 

Regarding your second question, please check the image below. As you can see ipg_clk_root comes straight from the core clock. All functionality inside the WDOG module is synchronized to ipg_clk_root so if core clock is missing WDOG will not work.

pastedImage_2.png

Have a great day,

Felipe

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mjbcswitzerland
Specialist V

Stefan

Write the data to RAM instead of Flash - mark the RAM with a signature that shows its content is valid.


Ensure that this is in a preserved area in RAM that is otherwise never used and it will be retained across the watchdog reset.

At each restart you can then check to see whether there was a watchdog reset that prepared data for you (also check the watchdog flash in the reset controller) and write it to flash now.

Regards

Mark

[uTasker project developer for Kinetis and i.MX RT]

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mitterha
Senior Contributor I

Thank you for your suggestion Mark, I will take a look into that solution!

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi Stefan,

 

I am sorry for the late reply. When handling interrupts it is always recommended to keep the handler as short as possible. Therefore is not recommended to write into flash inside IRQ.

 

Regarding your second question, please check the image below. As you can see ipg_clk_root comes straight from the core clock. All functionality inside the WDOG module is synchronized to ipg_clk_root so if core clock is missing WDOG will not work.

pastedImage_2.png

Have a great day,

Felipe

-------------------------------------------------------------------------------

Note:

- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored

Please open a new thread and refer to the closed one, if you have a related question at a later point in time

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mitterha
Senior Contributor I

Hello Felipe,

thank you for your answer!

If we use LPO as clock source for Watchdog 1 it will still not work if ipg_clock is off because the watchdog control logic is driven by ipg_clock_root right?

Kind regards,

Stefan

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FelipeGarcia
NXP TechSupport
NXP TechSupport

That is correct.

 

Regards,

Felipe

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mitterha
Senior Contributor I

Thank you!

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