Settings of FlexSPI clock root and USB1 PLL (PLL3) of ROM bootloader in case of NOR FLASH boot

[leopoldgemsch]

Dear all,

we are in setting up a project, based on the i.MX RT1051 MCU. The project runs the code out from attached NOR FLASH, connected on FlexSPI (FlexSPI NOR - QSPI 2nd Option).

So far all is working. With XIP_EXTERNAL_FLASH defined, the USB1 PLL (PLL3) and FlexSPI root clock are set by ROM bootloader, we do not have any configuration in the DCD setup.

The resulting configuration of clock configuration, with 60MHz as SPI clock selected in the boot settings (serialClkFreq=3), as we see according the register settings in debugger are:

• PLL3: 480MHz
• PLL3 PFD0: 360MHz
• PLL3 PFD1: 246.86MHz
• PLL3 PFD2: 332.31MHz
• PLL3 PFD3: 576MHz
• FlexSPI clock mux: 3 (set to clock source PLL3 PFD0)
• FlexSPI clock div: 5 (PLL3 PFD0 divided by 6 -> 60MHz)

Neither in the reference manual from i.MX RT1050 nor in application notes we could find this documented so far.

Does someone know or have the clock settings from ROM bootloader in case of NOR FLASH boot, also for the other selectable serial clock frequencies (especially for 100 / 133 MHz)?
Does NXP have a official documentation / application note about the clock settings from ROM bootloader?

For any helpful response many thanks

[mjbcswitzerland]

Hi

Do you mean the value to set in the flash configuration at

[0x046-0x046] serial flash frequency?

If so there is a set of defines as follows:

#define kFlexSpiSerialClk_30MHz 1
#define kFlexSpiSerialClk_50MHz 2
#define kFlexSpiSerialClk_60MHz 3
#define kFlexSpiSerialClk_75MHz 4
#define kFlexSpiSerialClk_80MHz 5
#define kFlexSpiSerialClk_100MHz 6
#define kFlexSpiSerialClk_133MHz 7
#define kFlexSpiSerialClk_166MHz 8
#define kFlexSpiSerialClk_200MHz 9

Also, from the FlexSPI configuration block in the i.MX Rt 1050 User's Manual:

See also the FlexSPI clock sections of https://www.utasker.com/docs/iMX/i.MX_RT_1021_uTasker.pdf and https://www.utasker.com/docs/iMX/i.MX_RT_1052_uTasker.pdf

Regards

Mark
[uTasker project developer for Kinetis and i.MX RT]
Contact me by personal message or on the uTasker web site to discuss professional training, solutions to problems or rapid product development requirements

For professionals searching for faster, problem-free Kinetis and i.MX RT 10xx developments the uTasker project holds the key: https://www.utasker.com/iMX/RT1050.html

[leopoldgemsch]

Dear Mark,

no this is not what I'm looking for.

How to configure the serial flash frequency is clear.

The ROM bootloader configures the PLL3 (also referred to USB1 PLL) and FlexSPI root clock.
Documentation of this configuration we are looking and it depends on configured serial flash frequency.

Best regards

[mjbcswitzerland · Accepted solution]

Hi

I see that you checked the way that the ROM LOADER did it for 60MHz (PLL3-PFD0 at 360MHz / 6 = 60MHz)

I also don't know of details as to how the ROM LOADER makes the decision and programs the best frequency but the fastest method to find out (if no one knows how to quickly locates the details) would be to set these values and recheck the settings for these cases too.

I suspect that it plays around with the PLL3-PFD0 frequency since 360MHz doesn't match with the default value in the user's manual (presumably it has changed this):

and also if it were to jump around to different sources (like the default SEMC_CLK_ROOT, which may in turn be dependent on PERIPH_CLK, there would be an increased risk of the QSPI flash operation failing when an application changed such settings).

Therefore my guess is that the value of PFD0_FRAC in CCM_ANALOG_PFD_480 will be modified according to the exact frequency required, whereby it can be set to generate the following values:

If you check the registers, including CCM_ANALOG_PFD_480 you probably will obtain the complete picture.

Regards

Mark