RT1170: MIPI Display Setup [DPHY PLL not locking]

[lsrbigfoot]

Hello,

I am attempting to get concepts from the emwin_gui_demo project to run on a custom PCBA (RT1172AVM8A MCU @ 800 MHz) with the RK055HDMIPI4MA0 MIPI display connected to the board. I am aware that RT1170 EVKB has the RT1176DVMAA running at 996 MHz.

The main problem I am seeing on custom PCBA is that the DPHY PLL never locks inside the function call DSI_InitDphy() [called by BOARD_SetMipiDsiConfig] after being configured with same parameters as RT1170 EVKB example. 

mipiDsiDpiClkFreq_Hz        = ~59MHz (58,666,666 Hz)
mipiDsiDphyBitClkFreq_Hz = ~792 MHz (791,999,991 Hz)
mipiDsiTxEscClkFreq_Hz    =  16 MHz
mipiDsiDphyRefClkFreq_Hz = 24 MHz

Interesting things is that RT1170 EVKB executes the DSI_InitDphy() call and changes mipiDsiDphyBitClkFreq_Hz  to exactly 792 MHz.

However, for my custom board DSI_InitDphy(), debugger shows outputPllFreq being corrected to 792 MHz but hangs in Lock wait loop.

What usually causes the DPHY PLL not to lock?
Do I need to use a different set of DSI frequencies with RT1172AVM8A running at 800 MHz in order for the DPHY to lock?

[lsrbigfoot · Accepted solution]

Just to provide an update, I got the DPHY PLL to lock after trying an alternative root clock configuration for the reference clock:

• Before: OSC 24 MHz / 1                        [as used by NXP EVKB]
• After: Video PLL (960 MHz) / 40            [Custom PCBA]