RT1160 SDK: clock_pll_post_div_t in file fsl_clock.h has the wrong enum values defined

[kyle81]

Please help to confirm if the enum values are wrong in file fsl_clock.h for RT1165 SDK ?

The current defines:

/*!

 * @brief PLL post divider enumeration.

 */

typedef enum _clock_pll_post_div

{

    kCLOCK_PllPostDiv8 = 0U, /*!< Divide by 8. */

    kCLOCK_PllPostDiv4 = 1U, /*!< Divide by 4. */

} clock_pll_post_div_t;

These values don't match the manual (15.9.4.2 ARM_PLL_CTRL_REG)

[kerryzhou]

Hi @kyle81 ,

  Please tell me your used SDK version, and your mentioned file name, then I will help to check it on my side, thanks.

Best Regards,

Kerry

[kyle81]

SDK version: SDK_2_14_0_MIMXRT1160-EVK

file: fsl_clock.h,

enum: clock_pll_post_div_t

[kerryzhou · Accepted solution]

Hi @kyle81 ,

  Thanks so much for your question and information.

   I agree with you, I also think it is the SDK code bug, I already report it to the internal SDK team.

  This code comment matches to the RM register:

In the demo,  didn't find the issue, because the :

kCLOCK_PllPostDiv4 =1 is the divide by 4

This is correct.

If you need other clock_pll_post_div_t data, you need to define:

typedef enum _clock_pll_post_div
{
    kCLOCK_PllPostDiv2 = 0U, /*!< Divide by 2. */
    kCLOCK_PllPostDiv4 = 1U, /*!< Divide by 4. */
    kCLOCK_PllPostDiv8 = 2U, /*!< Divide by 8. */
    kCLOCK_PllPostDiv1 = 3U, /*!< Divide by 1. */
} clock_pll_post_div_t;

In fact, I also checked the RT1170 SDK 2.14.0, that fsl_clock.h is correct:

I report to the SDK now, it will be fixed in the next SDK version.

Thanks so much for your contribution.

If you find and SDK issues, welcome to let us know, thanks.

Best Regards,

kerry