RT1061:POR_B signal and the power sequence question

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RT1061:POR_B signal and the power sequence question

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shaozhongliangs
NXP Employee
NXP Employee

 

In customer's PCBA, the POR_B signal is driven with a RC reset circuit. While in RT1060 EVK, the POR_B is controled with a reset supervisor IC(UM803RS @2.63V). Below is the waveform of power sequence on customer's board. Are there any potential issues that customer should careful?

shaozhongliangs_0-1688548818304.png

 

shaozhongliangs_1-1688548830724.png

 

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diego_charles
NXP TechSupport
NXP TechSupport

Hi @shaozhongliangs 

I hope you are doing great.

The best is to use an reset supervisor IC. See the below excerpt from AN13202
EMC Design Recommendation on i.MXRT Series

diego_charles_1-1688583091272.png

The potencial issues that I can see, with only having the RC circuit, is that you loose the power supply low voltage detection  and precise reset de-assert timing. Also, with the RC circuit, the system may be out of spec, POR_B is not actually asserted until the last supply rail reached its working voltage

The RC circuit may improve EMC performance, but it is not the recommended solution for POR_B. 

Additionally, In our EVK, the reset assert and de-assert looks like this when the during a Power on reset and SNVS wake up events. The reset is asserted with a considerable marging, more than 200 ms after the last rail booted.

diego_charles_3-1688583458411.png

 

All the best, 

Diego

 

 

 

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diego_charles
NXP TechSupport
NXP TechSupport

Hi @shaozhongliangs 

I hope you are doing great.

The best is to use an reset supervisor IC. See the below excerpt from AN13202
EMC Design Recommendation on i.MXRT Series

diego_charles_1-1688583091272.png

The potencial issues that I can see, with only having the RC circuit, is that you loose the power supply low voltage detection  and precise reset de-assert timing. Also, with the RC circuit, the system may be out of spec, POR_B is not actually asserted until the last supply rail reached its working voltage

The RC circuit may improve EMC performance, but it is not the recommended solution for POR_B. 

Additionally, In our EVK, the reset assert and de-assert looks like this when the during a Power on reset and SNVS wake up events. The reset is asserted with a considerable marging, more than 200 ms after the last rail booted.

diego_charles_3-1688583458411.png

 

All the best, 

Diego

 

 

 

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