Hi all,
I developed Custom board using IMX1052 and tried use S25FL512S external flash memory in QUAD mode.
I used nor pooling_transfer exemple to understand and study about LUT table.
I changed the example to put my memory in QUAD mode, enable Autoboot function, set region to
0x6000000 and did functions to read and verify if everything was written. I had just no have success in one test - page program, I can run single page program but It jumps first byte, in other words, It fails too.
Now I'm trying run hello word example in external nor flash.
I used AN12183 instructions without success, can you help me to find my fault ?
Env:
last version of MCUpresso and SDK on Windows 10 or OSX.
JLink Base - (Changed Xml to allow JLink flash QSPI NOR Flash)
Memory detail:
XIP detail:
Path and Symbols
After flash I have this behavior:
Console output:
SEGGER J-Link GDB Server V7.50a Command Line Version
JLinkARM.dll V7.50a (DLL compiled Jul 8 2021 18:16:55)
Command line: -nosilent -swoport 2334 -select USB=51009823 -jlinkscriptfile /Users/felipemdeo/Documents/MCUXpressoIDE_11.3.1/workspace/.mcuxpressoide_packages_support/MIMXRT1052xxxxB_support/Script/evkbimxrt1050_sdram_init.jlinkscript -telnetport 2335 -singlerun -endian little -noir -speed auto -port 2336 -vd -device MCIMXRT1052 -if SWD -halt -reportuseraction
-----GDB Server start settings-----
GDBInit file: none
GDB Server Listening port: 2336
SWO raw output listening port: 2334
Terminal I/O port: 2335
Accept remote connection: yes
Generate logfile: off
Verify download: on
Init regs on start: off
Silent mode: off
Single run mode: on
Target connection timeout: 0 ms
------J-Link related settings------
J-Link Host interface: USB
J-Link script: /Users/felipemdeo/Documents/MCUXpressoIDE_11.3.1/workspace/.mcuxpressoide_packages_support/MIMXRT1052xxxxB_support/Script/evkbimxrt1050_sdram_init.jlinkscript
J-Link settings file: none
------Target related settings------
Target device: MCIMXRT1052
Target interface: SWD
Target interface speed: auto
Target endian: little
Connecting to J-Link...
J-Link is connected.
Device "MIMXRT1052XXXXA" selected.
Firmware: J-Link V11 compiled Jun 29 2021 16:12:24
Hardware: V11.00
S/N: 51009823
Feature(s): GDB
Checking target voltage...
Target voltage: 3.35 V
Listening on TCP/IP port 2336
Connecting to target...
ConfigTargetSettings() start
Config JTAG Speed to 4000kHz
ConfigTargetSettings() end
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770041)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
ROMTbl[0][0]: E00FE000, CID: B105100D, PID: 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
ROMTbl[1][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
ROMTbl[2][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[2][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT
ROMTbl[2][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB-M7
ROMTbl[2][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM
ROMTbl[1][1]: E0041000, CID: B105900D, PID: 001BB975 ETM-M7
ROMTbl[1][2]: E0042000, CID: B105900D, PID: 004BB906 CTI
ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BB9A9 TPIU-M7
ROMTbl[0][2]: E0043000, CID: B105F00D, PID: 001BB101 TSG
Cache: Separate I- and D-cache.
I-Cache L1: 32 KiB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KiB, 256 Sets, 32 Bytes/Line, 4-Way
SetupTarget() start
Enabling i.MXRT SDRAM
FlexRAM configuration is restored
DCDC trim value loaded.
Clock Init Done
SDRAM Init Done
SetupTarget() end
ConfigTargetSettings() start
Config JTAG Speed to 4000kHz
ConfigTargetSettings() end
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
ROMTbl[0][0]: E00FE000, CID: B105100D, PID: 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
ROMTbl[1][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
ROMTbl[2][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[2][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT
ROMTbl[2][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB-M7
ROMTbl[2][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM
ROMTbl[1][1]: E0041000, CID: B105900D, PID: 001BB975 ETM-M7
ROMTbl[1][2]: E0042000, CID: B105900D, PID: 004BB906 CTI
ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BB9A9 TPIU-M7
ROMTbl[0][2]: E0043000, CID: B105F00D, PID: 001BB101 TSG
Cache: Separate I- and D-cache.
I-Cache L1: 32 KiB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KiB, 256 Sets, 32 Bytes/Line, 4-Way
SetupTarget() start
Enabling i.MXRT SDRAM
FlexRAM configuration is restored
DCDC trim value loaded.
Clock Init Done
SDRAM Init Done
SetupTarget() end
Connected to target
Waiting for GDB connection...Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x0020C73E (Data = 0x68602500)
Read 2 bytes @ address 0x0020C73E (Data = 0x2500)
Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x0020C73E (Data = 0x68602500)
Read 2 bytes @ address 0x0020C73E (Data = 0x2500)
Received monitor command: reset
ResetTarget() start
Core did not halt on reset vector. Assuming faulty image.
Resetting and halting core on image verification value read.
Core did not halt after reset step 1
ResetTarget() end
AfterResetTarget() start
FlexRAM configuration is restored
DCDC trim value loaded.
Clock Init Done
SDRAM Init Done
AfterResetTarget() end
Resetting target
Downloading 8192 bytes @ address 0x60000000 - Verified OK
Downloading 12320 bytes @ address 0x60002000 - Verified OK
Downloading 4 bytes @ address 0x60005020 - Verified OK
Hi @moura_fmo ,
Please run the SDK project:
SDK_2_10_0_EVKB-IMXRT1050\boards\evkbimxrt1050\driver_examples\flexspi\nor\polling_transfer
From the internal RAM, not the external flash.
Can you run code in RAM with your customer board and the JLINK?
Your QSPI chip QE is bit 1 of the status register 2.
So you need to modify the QE enable bit data.
#define FLASH_QUAD_ENABLE 0x200
Please let the RAM flexSPI code works at first, then switch to the code debug in FLASH.
Wish it helps you!
Best Regards,
kerry
Hi kerryzhou, tnx for your reply.
I can run most part flexspi_nor_polling_transfer.c example. I did some modifications to put QE bit in enable:
I defined FLASH_QUAD_ENABLE with 0x200 and change function to send 2 bytes (without it I had problem in sector erase) after write command. It is particularity from S25FL512 ->
I did function to read RDCR register and I got correct value:
Look my output, please:
So, code flow well, but I have error after run "flexspi_nor_flash_page_program"
For any reason, function finish but data is not written in memory.
Bellow follow my LUT command to Quad Page Program.
Bellow the result from "flexspi_nor_flash_page_program.
My definitions in app.h
Do you believe that I can try run in external memory or I need fully run this example before it.
If I need fully run this example, you have any tip to me to help understand where my fault?
