Hi,
We are looking into the performance of HyperRAM on the MIMXRT1180-EVK board. For this we have written a small application that performs some basic read and write operations from/to HyperRAM, for both sequential and random accesses and with cache enabled/disabled. Code is running from QuadSPI flash and HyperRAM is configured to run at 166 MHz (DDR).
To optimize data transfer, we have followed the application note AN12239 which was made for the MIMXRT1050-EVKB. This recommends to:
- Change the HyperRAM memory space type to the Normal mode in the MPU
- We have verified that in the default SDK, this is indeed the case:
- MPU->RBAR = ARM_MPU_RBAR(9, 0x04000000U);
- MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
- Enable the FlexSPI write access bufferable feature
- We have verified that AHBCR.BUFFERABLEEN = 1
- Enable the FlexSPI read access prefetch feature
- We have verified that AHBCR.PREFETCHEN = 1
- We have performed tests both with cache enabled and disabled
When running the tests with cache enabled and sequential data access, we have a read performance of 220 MB/s and write performance of 80 MB/s. With cache disabled, this becomes 100 MB/s for read and 50 MB/s for write. The write performance is thus much lower than mentioned in the application note.
My questions are:
- Do you know how the measurements in the application note were performed? The tables (4&5) mention "core" read/write performance. The measurements we did, were measured at application level.
- Are there other ways to improve the write performance for HyperRAM connected to FlexSPI or good practices we can take into account?
- Do you have some benchmark/throughput results for HyperRAM on i.MXRT118x/i.MXRT117x processors/boards?
Thank you for the information.
Tristan
i.MX-RT1180 MIMXRT1180-EVK
