Booting from NAND FLASH and Executing from HyperRAM Using MXRT1172

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Booting from NAND FLASH and Executing from HyperRAM Using MXRT1172

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LuisC
Contributor II

Hello,

I am currently working on a prototype board that contains an MXRT1172, a W25N01JW NAND FLASH chip, and a W959D8NFYA HyperRAM chip. The board is using FlexSPI2 to interact with the NAND boot device and FlexSPI1 to interact with the HyperRAM. Using the MCUXpresso IDE, I have created an application that blinks an LED on the board. So far, I have been able to run this application directly from the internal RAM of the processor by downloading it using SWD. I have also successfully used the MCUXpresso Secure Provisioning Tool (with a flashloader hardcoded for FlexSPI2) to flash the program into the NAND FLASH, copy it over to the internal RAM, and execute it from the internal RAM.

Now I need to flash the application into NAND FLASH again, but this time,copy and execute from the external HyperRAM on the board. In the (properties > C/C++Build > MCU settings) section of my project in the MCUXpresso IDE, I have added a new RAM memory at Location 0x30002000. I moved this memory to the top of the table. To get around the known issue where the secure provisioning tool interprets all images at a FlexSPI address as execute in place, I am building directly with the NXP elftosb tool by modifying my .bd file to the following:

options {
flags = 0x00;
startAddress = 0x30001000;
ivtOffset = 0x400;
initialLoadSize = 0x1000;
DCDFilePath = "..\..\configs\xmcd.bin";
entryPointAddress = 0x300024e9;
}

sources {
elfFile = extern(0);
}

section (0) {
}

I exchange the XMCDFilePath option for the DCDFilePath option because both the XMCDFilePath and DCDFilePath options load the file contents at offset 0x40 from ivtOffset.

The xmcd.bin file that I am using contains the following data: 08 00 00 C0 00 03 00 C0.

Using the .srec file of my project, I build the image. Once I create the Binary, I remove the DCD pointer that is created in the IVT.

The following are the contents of my IVT, Boot Data Structure, and XMCD in the generated bin file starting at address 00000400:

00000400 D1 00 20 40 E9 24 00 30 00 00 00 00 00 00 00 00

00000410 20 14 00 30 00 14 00 30 00 00 00 00 00 00 00 00

00000420 00 10 00 30 8C 88 00 00 00 00 00 00 00 00 00 00

00000430 00 10 00 30 8C 88 00 00 00 00 00 00 00 00 00 00

00000440 08 00 00 C0 00 03 00 C0 00 00 00 00 00 00 00 00

The application begins at address 00001000. There is no other data from addresses 00000000 - 00000ff0.

Using this bin file, I set up my Boot Memory Configuration in the Secure Provisioning Tool, the same way I did for when booting from Internal Ram, and write the image.

So far, I don't even see a clock signal going to the HyperRAM. Am I missing some information in my binary or have any incorrect data in my IVT, Boot Data Structure, or XMCD? Any information for why my application is not running would be greatly appreciated.

Thanks in advance.

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2 Replies

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @LuisC,

The following application note describes in detail everything you need to do in order to enable HyperRAM usage for i.MX RT devices: 

https://www.nxp.com/docs/en/nxp/application-notes/AN12239.pdf

This is the link to download the SW package for this AN: https://www.nxp.com/docs/en/nxp/application-notes-software/AN12239SW.zip

Please look into it and let me know if it helps.

 

PD: This other application note might also be useful for you: https://www.nxp.com/docs/en/application-note/AN13028.pdf

BR,
Edwin

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LuisC
Contributor II

Hello Edwin,

 

I have already been communicating with the HyperRAM using a modified version of the flexspi_nor_polling_transfer project. I was hoping there was a Full FlexSPI RAM Configuration Block structure you could provide that is compatible with my HyperRAM. So that I could include this in my boot image and the ROM could copy my application to the HyperRAM at boot.

 

Thanks.

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