iMX RT1170 Shared Memory

BTasdemir · ‎11-23-2023

Hi,

I split the OCRAM area. Im using 0x20338000 address for sharing datas. I write data from M4 core to this address and then I want to read same datas in same address. When I read from M4, I can see that the data has changed but when I read from M7, I cannot see that the data has changed. If I stop the code with a breakpoint, the data is updated.

jingpan · ‎11-24-2023

Hi @BTasdemir ,

I think it's most probably caused by cache. OCRAM is cacheable. And both M7 and M4 core has cache.

Regards,

Jing

BTasdemir · ‎11-24-2023

Hi @jingpan

Which ram region should I use for this ?

jingpan · ‎11-27-2023

Hi @BTasdemir ,

You can set the area to noncacheable. Please refer to the function BOARD_ConfigMPU().

Regards,

Jing